Abstract: An FRAM device can comprise a sense amplifier and at least a first bitcell. The first bitcell can have a bit line and a complimentary bit line that connects to the sense amplifier. A first precharge circuit responds to a first control signal during a test mode of operation to precharge the bit line with respect to a first voltage while a second precharge circuit responds to a second control signal (that is different from the first control signal) during the test mode of operation to precharge the complimentary bit line with respect to a test voltage that is different than the first voltage (such as, but not limited to, a test voltage of choice such as a voltage that is greater than ground but less than the first voltage).

Abstract: Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode and with write assist bias in a normal operating mode. The memory is constructed of multiple memory array blocks of SRAM cells. Bias devices are associated with each memory array block, and associated with one or more columns. Each bias device includes a diode-connected transistor in parallel with a shorting transistor, between a power supply voltage and a power supply bias node for cells in its column or columns. The shorting transistor receives control signals from control logic so that the diode-connected transistor for each column is shorted during read cycles, and in write cycles in which its columns are not selected; in write cycles in which its columns are selected, the shorting transistor in the bias device is turned off, so that a reduced power supply voltage is applied to the selected column. The shorting transistors for all columns in the block are turned off in the RTA mode.

Abstract: A system and are described as to adjusting voltages in a memory device, while the device is in sleep mode, to prevent or minimize voltage or current leakage of the device.

Abstract: A method and system are described for a two step precharging of bitlines in a memory array. In the first step a partial precharge of the bitline is accomplished with a lower power supply, the second step completes the bitline precharge with the higher power supply. Since the higher power supply must ultimately supply the final bitline precharge voltage achieving a partial bitline precharge with a lower power supply will result in lower sram and system power.

Abstract: A memory array is provided having a memory cell coupled to a read word line and a write word line of the memory array and peripheral circuits for reading and writing to the memory cell. The memory cell comprises a storage element for storing a logical state of the memory cell powered at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line in the memory array in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line.

Abstract: A memory array is provided having a memory cell coupled to a read word line and a write word line of the memory array and peripheral circuits for reading and writing to the memory cell. The memory cell comprises a storage element for storing a logical state of the memory cell powered at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line in the memory array in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line.

Abstract: An exemplary system and methods implementing pulse width control in SRAM bit cell arrays that vary in size are described.

Abstract: A memory array is provided having a memory cell coupled to a read word line and a write word line of the memory array and peripheral circuits for reading and writing to the memory cell. The memory cell comprises a storage element for storing a logical state of the memory cell powered at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line in the memory array in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line.

Abstract: The present invention describes circuitry and a method of providing a low power WRITE mode of operation for an integrated circuit comprising an SRAM memory to provide a reduced IDDQ relative to the IDDQ of a full active mode. In one aspect, the circuitry includes an SRAM memory array, mode control circuitry coupled to the array and configured to alter a supply voltage level to the SRAM array based on a mode of operation. The circuitry also includes control inputs coupled to the mode control circuitry for selecting one of the low power write mode, the full active mode, and optionally a retention mode of operation. The mode control circuitry is configured to receive the control inputs to select one of the three modes of operation, and to alter one or more supply voltage levels to the array, for example, the Vss supply voltage using a Vss supply circuit and the Vdd supply voltage using a Vdd supply circuit, based on the selected mode of operation.

Abstract: The present invention describes circuitry and a method of providing a low power WRITE mode of operation for an integrated circuit comprising an SRAM memory to provide a reduced IDDQ relative to the IDDQ of a full active mode. In one aspect, the circuitry includes an SRAM memory array, mode control circuitry coupled to the array and configured to alter a supply voltage level to the SRAM array based on a mode of operation. The circuitry also includes control inputs coupled to the mode control circuitry for selecting one of the low power write mode, the full active mode, and optionally a retention mode of operation. The mode control circuitry is configured to receive the control inputs to select one of the three modes of operation, and to alter one or more supply voltage levels to the array, for example, the Vss supply voltage using a Vss supply circuit and the Vdd supply voltage using a Vdd supply circuit, based on the selected mode of operation.

Abstract: A system and are described as to adjusting voltages in a memory device, while the device is in sleep mode, to prevent or minimize voltage or current leakage of the device.

Abstract: A method and system are described for a two step precharging of bitlines in a memory array. In the first step a partial precharge of the bitline is accomplished with a lower power supply, the second step completes the bitline precharge with the higher power supply. Since the higher power supply must ultimately supply the final bitline precharge voltage achieving a partial bitline precharge with a lower power supply will result in lower sram and system power.

Abstract: A system and are described as to adjusting voltages in a memory device, while the device is in sleep mode, to prevent or minimize voltage or current leakage of the device.

Abstract: The present invention describes circuitry and a method of providing a low power WRITE mode of operation for an integrated circuit comprising an SRAM memory to provide a reduced IDDQ relative to the IDDQ of a full active mode. In one aspect, the circuitry includes an SRAM memory array, mode control circuitry coupled to the array and configured to alter a supply voltage level to the SRAM array based on a mode of operation. The circuitry also includes control inputs coupled to the mode control circuitry for selecting one of the low power write mode, the full active mode, and optionally a retention mode of operation. The mode control circuitry is configured to receive the control inputs to select one of the three modes of operation, and to alter one or more supply voltage levels to the array, for example, the Vss supply voltage using a Vss supply circuit and the Vdd supply voltage using a Vdd supply circuit, based on the selected mode of operation.

Abstract: A high speed/narrow I/O DRAM device comprises both a data input/output (I/O) port as well as a command port for receiving commands used to control the operations of the DRAM. The command port is defined as input only (i.e., for inputting command data). The present invention comprises multiplexing write data to be written and stored in the DRAM onto the command port with command data packets. The data I/O port can then become dedicated to streaming out seamless data since it no longer needs to flip between input and output data. Even greater bus efficiency can be realized if, during a command packet transfer, data writes to the DRAM are switched back to the data I/O port. With this input port switching protocol, greater bus efficiency and increased memory performance can be realized.