Patents by Inventor Michael Pedneau

Michael Pedneau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6304944
    Abstract: A method and apparatus for improving the efficiency of the cacheability (and other attribute) determination by making the information from the region register available during linear to physical address translation, rather than serially upon completion of the address translation. Address range comparisons are made when the TLB is loaded. That is, attribute information stored in a region register or registers is compared with physical addresses corresponding to translations loaded in a translation lookaside buffer reload operation. The present invention thus advantageously removes the region register compare operation from the path to memory.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: October 16, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Michael Pedneau
  • Patent number: 6189074
    Abstract: A method and apparatus for improving the efficiency of the cacheability (and other attribute) determination by making the information from the region register available during linear to physical address translation, rather than serially upon completion of the address translation. Address range comparisons are made when the TLB is loaded. That is, attribute information stored in a region register or registers is compared with physical addresses corresponding to translations loaded in a translation lookaside buffer reload operation. The present invention thus advantageously removes the region register compare operation from the path to memory.
    Type: Grant
    Filed: March 19, 1997
    Date of Patent: February 13, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Michael Pedneau