Patents by Inventor Michael Peeters
Michael Peeters has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240103873Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.Type: ApplicationFiled: December 7, 2023Publication date: March 28, 2024Applicants: STMICROELECTRONICS (ROUSSET) SAS, PROTON WORLD INTERNATIONAL N.V.Inventors: Michael PEETERS, Fabrice MARINET
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Patent number: 11853765Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.Type: GrantFiled: April 14, 2022Date of Patent: December 26, 2023Assignees: STMICROELECTRONICS (ROUSSET) SAS, PROTON WORLD INTERNATIONAL N.V.Inventors: Michael Peeters, Fabrice Marinet
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Patent number: 11831771Abstract: Cryptographic circuitry, in operation, generates N first pairs of elliptic curve cryptography (ECC) keys r(i), R(i), with i varying from 1 to N, using K second pairs of ECC keys p(k), P(k), with k varying from 1 to K, wherein K is smaller than N. Each pair r(i), R(i) of the first pairs of keys is a linear combination of pairs of the second pairs of ECC keys according to: ? i ? [ 1 ; N ] ? { r ? ( l ) = ? j = 1 K A ? ( i , j ) * p ? ( j ) R ? ( i ) = ? j = 1 K A ? ( i , j ) * P ? ( j ) , wherein A(i,j) designates a general term of a matrix A of size N*K, and all the sub-matrices of size K*K are invertible. The cryptographic circuitry, in operation, executes cryptographic operations using one or more pairs of the first pairs of ECC keys.Type: GrantFiled: October 20, 2021Date of Patent: November 28, 2023Assignees: STMICROELECTRONICS S.r.l., PROTON WORLD INTERNATIONAL N.V.Inventors: Thierry Simon, Michael Peeters, Francesco Caserta
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Patent number: 11776601Abstract: The present disclosure relates to a monotonic counter whose value is represented by a number N of binary words of N memory cells of a non-volatile memory, and being able to implement a step increment operation wherein if only one first memory cell represents a first value different from zero, then a second value equal to the said first value incremented by two times the said step is written into a second memory cell of rank directly higher than the rank of the first memory cell; and if a third and a fourth memory cell of consecutive ranks represent, respectively, a third value and a fourth value different from zero, then the third value of the third memory cell of lower rank is erased.Type: GrantFiled: March 10, 2022Date of Patent: October 3, 2023Assignee: PROTON WORLD INTERNATIONAL N.V.Inventors: Jean-Louis Modave, Michael Peeters, Ronny Van Keer
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Publication number: 20230259607Abstract: The present disclosure relates to an authentication method of a first device by a second device, each first, second device having a processor, at least one memory, and an authentication circuit, in which the authentication circuit is configured to prohibit the processor from reading data stored in at least part of said memory. The authenticating includes generating a first datum, and a second datum. The second device verifies that the first and second data match.Type: ApplicationFiled: April 24, 2023Publication date: August 17, 2023Applicant: PROTON WORLD INTERNATIONAL N.V.Inventors: Jean-Louis MODAVE, Michael PEETERS
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Patent number: 11715506Abstract: A monotonic counter stores N binary words representing a value in N memory cells. When i memory cells of consecutive ranks between k modulo N and k+i modulo N each represent a value complementary to a null value, the counter is incremented by erasing a value of a memory cell of rank k+i+1 modulo N. When i+1 memory cells of consecutive ranks between k+1 modulo N and k+i+1 modulo N each represent the value complementary to the null value, the counter is incremented by incrementing a value of a memory cell of rank k modulo N by two step sizes and storing a result in a memory cell of rank k+1 modulo N, wherein, N is an integer greater than or equal to five, k is an integer, and i is an integer between 2 and N?3.Type: GrantFiled: March 10, 2022Date of Patent: August 1, 2023Assignee: PROTON WORLD INTERNATIONAL N.V.Inventors: Michael Peeters, Jean-Louis Modave, Ronny Van Keer
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Patent number: 11669610Abstract: The present disclosure relates to an authentication method of a first device by a second device, each first, second device having a processor, at least one memory, and an authentication circuit, in which the authentication circuit is configured to prohibit the processor from reading data stored in at least part of said memory. The authenticating includes generating a first datum, and a second datum. The second device verifies that the first and second data match.Type: GrantFiled: April 6, 2021Date of Patent: June 6, 2023Assignee: PROTON WORLD INTERNATIONAL N.V.Inventors: Jean-Louis Modave, Michael Peeters
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Patent number: 11651064Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and at least one previously-executed opcode.Type: GrantFiled: March 27, 2020Date of Patent: May 16, 2023Assignees: STMICROELECTRONICS (ROUSSET) SAS, PROTON WORLD INTERNATIONAL N.V.Inventors: Michael Peeters, Fabrice Marinet
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Patent number: 11494480Abstract: A first circuit is authenticated using a second circuit. A first datum and a second datum are stored in the second circuit. The second datum corresponds to an application of a first function to the first datum and a third datum. The second circuit sends the second datum to the first circuit. The first circuit decrypts the second datum and sends a fourth datum representative of a result of the decrypting to the first second circuit for authentication. The second circuit verifies a correspondence between the first datum and the fourth datum.Type: GrantFiled: February 21, 2020Date of Patent: November 8, 2022Assignee: PROTON WORLD INTERNATIONAL N.V.Inventor: Michael Peeters
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Publication number: 20220327064Abstract: The present disclosure relates to secure storage, in a non-volatile memory, of initial data encrypted using a second data, including selecting a pointer aimed at an initial address of a memory cell of an initial part of the non-volatile memory, and encrypting the pointer using the second data; and-storing the encrypted pointer in the non-volatile memory.Type: ApplicationFiled: March 3, 2022Publication date: October 13, 2022Inventor: Michael Peeters
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Publication number: 20220327194Abstract: The present disclosure relates to authenticating a first device to a second device, including at least two successive verification operations comprising the following successive steps. The second device generates a first data, and sends the first data to the first device. The first device generates a third data and a fourth data used by the following verification operation and sends the third data to the second device. The second device checks the third data indicating whether the check was successful or not.Type: ApplicationFiled: March 9, 2022Publication date: October 13, 2022Inventor: Michael Peeters
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Publication number: 20220293151Abstract: The present disclosure relates to a monotonic counter whose value is represented by a number N of binary words of N memory cells of a non-volatile memory, and being able to implement a step increment operation wherein if only one first memory cell represents a first value different from zero, then a second value equal to the said first value incremented by two times the said step is written into a second memory cell of rank directly higher than the rank of the first memory cell; and if a third and a fourth memory cell of consecutive ranks represent, respectively, a third value and a fourth value different from zero, then the third value of the third memory cell of lower rank is erased.Type: ApplicationFiled: March 10, 2022Publication date: September 15, 2022Applicant: PROTON WORLD INTERNATIONAL N.V.Inventors: Jean-Louis MODAVE, Michael PEETERS, Ronny VAN KEER
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Publication number: 20220293150Abstract: A monotonic counter stores N binary words representing a value in N memory cells. When i memory cells of consecutive ranks between k modulo N and k+i modulo N each represent a value complementary to a null value, the counter is incremented by erasing a value of a memory cell of rank k+i+1 modulo N. When i+1 memory cells of consecutive ranks between k+1 modulo N and k+i+1 modulo N each represent the value complementary to the null value, the counter is incremented by incrementing a value of a memory cell of rank k modulo N by two step sizes and storing a result in a memory cell of rank k+1 modulo N, wherein, N is an integer greater than or equal to five, k is an integer, and i is an integer between 2 and N?3.Type: ApplicationFiled: March 10, 2022Publication date: September 15, 2022Applicant: PROTON WORLD INTERNATIONAL N.V.Inventors: Michael PEETERS, Jean-Louis MODAVE, Ronny VAN KEER
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Publication number: 20220244961Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.Type: ApplicationFiled: April 14, 2022Publication date: August 4, 2022Applicants: STMICROELECTRONICS (ROUSSET) SAS, PROTON WORLD INTERNATIONAL N.V.Inventors: Michael PEETERS, Fabrice MARINET
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Patent number: 11379238Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.Type: GrantFiled: March 27, 2020Date of Patent: July 5, 2022Assignees: PROTON WORLD INTERNATIONAL N.V., STMICROELECTRONICS (ROUSSET) SASInventors: Michael Peeters, Fabrice Marinet
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Publication number: 20220141016Abstract: Cryptographic circuitry, in operation, generates N first pairs of elliptic curve cryptography (ECC) keys r(i), R(i), with i varying from 1 to N, using K second pairs of ECC keys p(k), P(k), with k varying from 1 to K, wherein K is smaller than N. Each pair r(i), R(i) of the first pairs of keys is a linear combination of pairs of the second pairs of ECC keys according to: ? ? i ? [ 1 ; N ] ? { r ? ( l ) = ? j = 1 K ? A ? ( i , j ) * p ? ( j ) R ? ( i ) = ? j = 1 K ? A ? ( i , j ) * P ? ( j ) , wherein A(i,j) designates a general term of a matrix A of size N*K, and all the sub-matrices of size K*K are invertible. The cryptographic circuitry, in operation, executes cryptographic operations using one or more pairs of the first pairs of ECC keys.Type: ApplicationFiled: October 20, 2021Publication date: May 5, 2022Applicants: STMICROELECTRONICS S.r.l., PROTON WORLD INTERNATIONAL N.V.Inventors: Thierry SIMON, Michael PEETERS, Francesco CASERTA
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Patent number: 11200936Abstract: A volatile memory circuit includes a first flip-flop, a second flip-flop having a set input coupled to an output of the first flip-flop. Logic circuitry of the memory circuit logically combines an output of the second flip-flop and information representative of the output of the first flip-flop to generate an output of the memory circuit. In response to a read command, the first flip-flop is reset and content of the second flip-flop is output by the circuit.Type: GrantFiled: December 9, 2019Date of Patent: December 14, 2021Assignee: PROTON WORLD INTERNATIONAL N.V.Inventor: Michael Peeters
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Publication number: 20210319089Abstract: The present disclosure relates to an authentication method of a first device by a second device, each first, second device having a processor, at least one memory, and an authentication circuit, in which the authentication circuit is configured to prohibit the processor from reading data stored in at least part of said memory. The authenticating includes generating a first datum, and a second datum. The second device verifies that the first and second data match.Type: ApplicationFiled: April 6, 2021Publication date: October 14, 2021Inventors: Jean-Louis MODAVE, Michael PEETERS
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Patent number: 11049567Abstract: A memory includes a rewritable non-volatile memory cell and input circuitry coupled to the memory cell. The input circuitry, in operation, erases the memory cell in response to reception of a request to read the memory cell. Similarly, a read-once memory includes an addressable, non-volatile memory having a plurality of rewriteable memory cells. Input circuitry coupled to the non-volatile memory responds to reception of a request to read content stored at an address in the non-volatile memory by erasing the content stored at the address of the non-volatile memory.Type: GrantFiled: December 9, 2019Date of Patent: June 29, 2021Assignee: PROTON WORLD INTERNATIONAL N.V.Inventor: Michael Peeters
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Patent number: 11025426Abstract: The disclosure concerns an encryption function applied to a first word, a second word, a third word, and a fourth word including: multiplying the third word by the fourth word; adding the result of the multiplication; subtracting the result of the addition to the second word from the result of the addition to the first word; adding the result of the subtraction; combining with a constant the result of the addition of the third word to the result of the subtraction; and multiplying by two the result of said combination and circularly shifting the codes of the respective results of the addition of the fourth word to the result of the subtraction, of the addition of the second word to the result of the multiplication, and of the addition of the first word to the result of the multiplication.Type: GrantFiled: January 16, 2019Date of Patent: June 1, 2021Assignee: PROTON WORLD INTERNATIONAL N.V.Inventors: Joan Daemen, Michael Peeters