Patents by Inventor Michael Peeters
Michael Peeters has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12657315Abstract: Various examples in accordance with the present disclosure provide example methods, systems, and apparatuses for data encryption.Type: GrantFiled: October 9, 2023Date of Patent: June 16, 2026Assignee: STMicroelectronics BelgiumInventor: Michael Peeters
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Publication number: 20260163724Abstract: A logic circuit includes an interface to communicate with a host, a processor, and a memory. The memory stores instructions that when executed by the processor cause the processor to, in response to a first start session command without having previously derived a shared key with the host, communicate with the host through a pairing channel where communications are authenticated using a session key derived from a pairing base key, to derive the shared key. The memory stores further instructions that when executed by the processor cause the processor to, in response to the first start session command and after having derived the shared key, communicate with the host through a nominal channel where communications are authenticated using a session key derived from the shared key.Type: ApplicationFiled: April 16, 2025Publication date: June 11, 2026Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Stephen D. Panshin, Jefferson P. Ward, Kyle L. Michel, Michael Peeters
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Patent number: 12650844Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.Type: GrantFiled: December 7, 2023Date of Patent: June 9, 2026Assignees: STMICROELECTRONICS (ROUSSET) SAS, STMICROELECTRONICS BELGIUMInventors: Michael Peeters, Fabrice Marinet
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Publication number: 20260119639Abstract: A method of authenticating a first device to a second device, where the first device stores a first list of data groups, includes the following steps: a) sending, by the second device to the first device, a second list of information relative to data; b) sending, by the first device to the second device, a third list of images, by a first function, of data of said first list of data groups, having as information that of said second list of information relative to data; and c) verifying, by the second device, whether the images of the data of said third list of images comply with the data of a fourth list of data groups corresponding to the image of the first list of data groups by a second function having its information comprised in the second list of information relative to data.Type: ApplicationFiled: October 27, 2025Publication date: April 30, 2026Applicant: STMicroelectronics International N.V.Inventors: Thierry SIMON, Michael PEETERS
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Patent number: 12566651Abstract: The present description concerns a method of checking a first data element, executed by an electronic device comprising a processor and a memory, wherein the first data element is divided in N second data elements being stored in the memory, and first data element being equal to the sum, modulo the dimension of a space comprising the first data element, of the N second data elements, wherein an image of the first data element by a LCG function is stored in the memory, and the method comprising a step of checking if the image of the first data element by the LCG function is equal to the sum, modulo the module of the LCG function, of a product of an integer varying from 0 to N?1 and an image of the dimension by the LCG function, and of the images of the second data elements by the LCG function.Type: GrantFiled: March 21, 2024Date of Patent: March 3, 2026Assignee: STMicroelectronics International N.V.Inventors: Michael Peeters, Pierre-Alexandre Blanc
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Publication number: 20260003950Abstract: The present description concerns a method of authenticating a first device to a second device, comprising the following successive steps: sending, by said second device, to said first device, of at least a first data item; use, by said first device, of a first neural network to deliver a second data item based on said at least one first data item; and sending, by said first device, of said second data item to said second device.Type: ApplicationFiled: June 17, 2025Publication date: January 1, 2026Applicant: STMicroelectronics International N.V.Inventor: Michael PEETERS
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Publication number: 20250284413Abstract: A method of verifying writing of data into a memory includes a step of verifying whether a last group of data written into the memory includes at least one sensitive data item. When the last group of data includes at least one sensitive data item, a first group of data is erased from the memory. At least one address of that first group of data is indicated in at least one first metadata item of a data item of said last group of data.Type: ApplicationFiled: March 5, 2025Publication date: September 11, 2025Applicant: STMicroelectronics International N.V.Inventors: Guillaume DOCQUIER, Michael PEETERS
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Publication number: 20250247236Abstract: A logic circuitry package includes an interface to communicate with a host logic circuit and a logic circuit. The logic circuit is configured to store or generate a plurality of tokens corresponding to respective token indices. The logic circuit is configured to receive at least one challenge command from the host logic circuit including a subset of token indices. The logic circuit is configured to in response to the at least one challenge command, transmit a list of data including a subset of tokens of the plurality of tokens corresponding to the received subset of token indices.Type: ApplicationFiled: April 18, 2025Publication date: July 31, 2025Applicant: Hewlett-Packard Development Company, L.P.Inventors: Stephen D. Panshin, Jefferson P. Ward, Michael Peeters
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Patent number: 12362922Abstract: An electronic device includes processing circuitry and one or more memories, including a non-volatile memory. Ephemeral cryptographic key generation circuitry, in operation, applies a function to code stored in the non-volatile memory, generating an ephemeral cryptographic key. Cryptographic circuitry coupled between the processing circuitry and the one or more memories, in operation, performs one or more cryptographic operations on data using the generated ephemeral cryptographic key. The device may include a register, which, in operation, temporarily stores the generated ephemeral cryptographic key.Type: GrantFiled: March 19, 2020Date of Patent: July 15, 2025Assignees: STMICROELECTRONICS (ROUSSET) SAS, STMICROELECTRONICS BELGIUMInventors: Fabrice Marinet, Michael Peeters
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Publication number: 20250217499Abstract: A cryptographic operation is protected. The protecting includes performing a matrix transformation operation on a matrix having n rows and n columns, each row forming a respective vector of a first set of ordered vectors. A second set of ordered vectors is generated by shifting values of vectors of the first set of ordered vectors in a first direction, wherein a pitch of a shift applied to a vector of the first set of ordered vectors is based on an order number of the vector of the first set of ordered vectors. A working vector is generated by logically combining vectors of the second set of ordered vectors. A third set of ordered vectors is generated based on the second set of ordered vectors. A fourth set of ordered vectors is generated based on the third set of ordered vectors and the working vector.Type: ApplicationFiled: December 16, 2024Publication date: July 3, 2025Applicant: STMicroelectronics International N.V.Inventors: Pierre-Alexandre BLANC, Michael PEETERS
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Publication number: 20250173420Abstract: A method of authentication of a first device to a second device uses a signature of an analog signal of the first device. The signature corresponds to a time variation of at least one physical quantity associated with the analog signal during the implementation of at least one specific operation. The at least one specific operation may be an implementation of an electronic function or a program.Type: ApplicationFiled: November 20, 2024Publication date: May 29, 2025Applicant: STMicroelectronics International N.V.Inventors: Michael PEETERS, Francois DE ROCHEBOUET, Jean-Louis MODAVE
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Publication number: 20250117499Abstract: Various examples in accordance with the present disclosure provide example methods, systems, and apparatuses for data encryption.Type: ApplicationFiled: October 9, 2023Publication date: April 10, 2025Inventor: Michael PEETERS
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AUTHENTICATION METHOD FOR USE IN PAIRING A PERIPHERAL DEVICE TO A COMPANION DEVICE VIA A HOST DEVICE
Publication number: 20250024265Abstract: An authentication method can be performed in view of a pairing of a peripheral device to a companion device via a host device. The method includes initiating a pairing session and, in response to the initiating, receiving a first command by the host device. The first command comprises a first command code and a first encrypted payload to be exchanged between the peripheral device and the companion device via the host device. The first command code indicates to the host device to transfer the first command without decoding it.Type: ApplicationFiled: July 11, 2023Publication date: January 16, 2025Inventors: Michael Peeters, Stephen D. Panshin -
Patent number: 12189754Abstract: The present disclosure relates to authenticating a first device to a second device, including at least two successive verification operations comprising the following successive steps. The second device generates a first data, and sends the first data to the first device. The first device generates a third data and a fourth data used by the following verification operation and sends the third data to the second device. The second device checks the third data indicating whether the check was successful or not.Type: GrantFiled: March 9, 2022Date of Patent: January 7, 2025Assignee: STMicroelectronics BelgiumInventor: Michael Peeters
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Publication number: 20240320074Abstract: The present description concerns a method of checking a first data element, executed by an electronic device comprising a processor and a memory, wherein the first data element is divided in N second data elements being stored in the memory, and first data element being equal to the sum, modulo the dimension of a space comprising the first data element, of the N second data elements, wherein an image of the first data element by a LCG function is stored in the memory, and the method comprising a step of checking if the image of the first data element by the LCG function is equal to the sum, modulo the module of the LCG function, of a product of an integer varying from 0 to N?1 and an image of the dimension by the LCG function, and of the images of the second data elements by the LCG function.Type: ApplicationFiled: March 21, 2024Publication date: September 26, 2024Applicant: STMicroelectronics International N.V.Inventor: Michael PEETERS
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Publication number: 20240281384Abstract: The present disclosure relates to secure storage, in a non-volatile memory, of initial data encrypted using a second data, including selecting a pointer aimed at an initial address of a memory cell of an initial part of the non-volatile memory, and encrypting the pointer using the second data; and-storing the encrypted pointer in the non-volatile memory.Type: ApplicationFiled: April 25, 2024Publication date: August 22, 2024Inventor: Michael Peeters
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Patent number: 12050703Abstract: An authentication method is used in pairing a peripheral device to a companion device. The peripheral device sends a first identifier and a first value of a first counter to the companion device. The companion device verifies whether a pairing table stored in the companion device contains the first identifier. When the pairing table does not include the first identifier the companion device initiates a pairing session. When the pairing table includes the first identifier, the companion device compares the first value to a second value associated with the first identifier in the pairing table. In response to the first value being greater than the second value, the companion devices initiates a nominal session and in response to the first value being lower than or equal to the second value, execution of the method is stopped.Type: GrantFiled: July 11, 2023Date of Patent: July 30, 2024Assignee: STMicroelectronics International N.V.Inventors: Michael Peeters, Stephen D. Panshin, Jefferson P. Ward, Kyle L. Michel
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Patent number: 12045334Abstract: The present disclosure relates to an authentication method of a first device by a second device, each first, second device having a processor, at least one memory, and an authentication circuit, in which the authentication circuit is configured to prohibit the processor from reading data stored in at least part of said memory. The authenticating includes generating a first datum, and a second datum. The second device verifies that the first and second data match.Type: GrantFiled: April 24, 2023Date of Patent: July 23, 2024Assignee: PROTON WORLD INTERNATIONAL N.V.Inventors: Jean-Louis Modave, Michael Peeters
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Patent number: 12001347Abstract: The present disclosure relates to secure storage, in a non-volatile memory, of initial data encrypted using a second data, including selecting a pointer aimed at an initial address of a memory cell of an initial part of the non-volatile memory, and encrypting the pointer using the second data; and-storing the encrypted pointer in the non-volatile memory.Type: GrantFiled: March 3, 2022Date of Patent: June 4, 2024Assignee: PROTON WORLD INTERNATIONAL N.V.Inventor: Michael Peeters
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Publication number: 20240103873Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.Type: ApplicationFiled: December 7, 2023Publication date: March 28, 2024Applicants: STMICROELECTRONICS (ROUSSET) SAS, PROTON WORLD INTERNATIONAL N.V.Inventors: Michael PEETERS, Fabrice MARINET