Abstract: A phase locked loop (PLL) lock detector may be configured to observe the phase error signal from a phase comparator of a PLL circuit. The PLL lock detector may accumulate a sum of phase errors and compare the sum of phase errors to determine whether the PLL circuit is locked in phase with the reference signal. Various modifications to the phase error signal and sum of phase errors may be used to improve the efficiency of the PLL lock detector. Configurable settings for the accumulator and a comparator may be used to adjust the operation of the PLL lock detector.

Abstract: A mechanism can be implemented in a communication unit of a network device to utilize periods of silence encountered in voice communication to conserve power at the network device. In some embodiments, it can be determined that one or more packets of a received RF signal comprise audio data. The communication unit of the network device can determine whether the audio data associated with the one or more packets comprises voice information. The network device can switch to a power save mode based, at least in part, on determining that the audio data associated with the one or more packets does not comprise voice information.

Abstract: A tri-state control mechanism can be implemented for a line driver of a transmitter unit to switch the output impedance of the transmitter unit between a low impedance state in the transmit mode and a high impedance state in the receive mode while minimizing turn-off glitch. It may be determined whether a communication device comprising the transmitter unit is configured in a transmit operating mode or a receive operating mode. If the communication device is configured in the receive operating mode, a first bias voltage can be generated to bias output transistors of the line driver circuit in a sub-threshold state. If the communication device is configured in the transmit operating mode, a second bias voltage can be generated to bias output transistors of the line driver circuit in a saturation state.

Abstract: A hybrid SAR ADC can be implemented to reduce the number of operations that are executed to convert an analog input signal into its digital representation. Pipeline processing operations can be executed on the analog input signal to generate pipeline bits (MSBs of the digital representation) and an analog residue signal. The analog residue signal can be compared against a plurality of thresholds to generate comparator bits that are indicative of a range associated with a subset of the predetermined thresholds that correspond to the analog residue signal. Successive approximation analog-to-digital conversion operations can be executed on the analog residue signal to generate successive approximation bits. The digital representation can be determined based, at least in part, on the pipeline bits, the comparator bits, and the successive approximation bits.

Abstract: A hybrid SAR ADC can be implemented to reduce the number of operations that are executed to convert an analog input signal into its digital representation. Pipeline processing operations can be executed on the analog input signal to generate pipeline bits (MSBs of the digital representation) and an analog residue signal. The analog residue signal can be compared against a plurality of thresholds to generate comparator bits that are indicative of a range associated with a subset of the predetermined thresholds that correspond to the analog residue signal. Successive approximation analog-to-digital conversion operations can be executed on the analog residue signal to generate successive approximation bits. The digital representation can be determined based, at least in part, on the pipeline bits, the comparator bits, and the successive approximation bits.

Abstract: A tri-state control mechanism can be implemented for a line driver of a transmitter unit to switch the output impedance of the transmitter unit between a low impedance state in the transmit mode and a high impedance state in the receive mode while minimizing turn-off glitch. It may be determined whether a communication device comprising the transmitter unit is configured in a transmit operating mode or a receive operating mode. If the communication device is configured in the receive operating mode, a first bias voltage can be generated to bias output transistors of the line driver circuit in a sub-threshold state. If the communication device is configured in the transmit operating mode, a second bias voltage can be generated to bias output transistors of the line driver circuit in a saturation state.

Abstract: A mechanism can be implemented in a communication unit of a network device to utilize periods of silence encountered in voice communication to conserve power at the network device. In some embodiments, it can be determined that one or more packets of a received RF signal comprise audio data. The communication unit of the network device can determine whether the audio data associated with the one or more packets comprises voice information. The network device can switch to a power save mode based, at least in part, on determining that the audio data associated with the one or more packets does not comprise voice information.

Abstract: A low drop out voltage regulator (LDO) is capable of operating in one of two different modes based on externally connected components. In one mode, the LDO directly generates a regulated output voltage. In a second mode, the LDO drives an external PNP transistor to generate a regulated output voltage. In both modes, a relatively large bypass capacitor may be connected to the output voltage node to bypass high-frequency loading on the output voltage node. However, the bypass capacitor creates a low frequency pole in the frequency response of the LDO, which can diminish phase margin and reduce overall stability. An on chip compensation network beneficially counteracts the low frequency pole with an appropriately placed zero, thereby resulting in improved phase margin and greater stability.

Abstract: A compact constant current generator that can operate with a positive supply voltage of 1.22 V (or lower) and minimize noise is provided. The constant current generator can include a bandgap reference circuit and a single gain stage. Notably, the bandgap reference circuit can advantageously generate differential node voltages. The gain stage can amplify those differential node voltages and generate a constant current having a temperature coefficient substantially equal to zero. Advantageously, this single gain stage can minimize the number of components, thereby resulting in a compact and efficient current generator.

Abstract: A phase selector for selecting a differential output is provided. The phase selector can include two matched transistor circuits. A first transistor circuit can receive a first differential input signal whereas a second transistor circuit can receive a second differential input signal. One of the transistor circuits can be used to dump an output current generated by the first differential input signal to Vdd. The other transistor circuit can be used to steer an output current generated by the second differential input signal to two output lines, thereby providing a differential output signal on the output lines.

Abstract: A single-chip CMOS direct conversion transceiver includes an RF circuit, a transmitter having a synthesizer, a receiver having a baseband filter, and a demodulator. The synthesizer is coupled to the RF circuit. The baseband filter is coupled to the RF circuit and the synthesizer. The demodulator is coupled to the baseband filter. The RF circuit, the synthesizer, the baseband filter, and the demodulator are arranged and configured in CMOS devices and provide a complete interface between an antenna and a voiceband codec.

Abstract: A common mode bias voltage generator apparatus and method includes a plurality of MOSFET-based transistors and a plurality of resistors configured and arranged to provide a half of a supply voltage with a predetermined low output impedance while using relatively little power and circuit area.

Abstract: A common mode bias voltage generator apparatus and method includes a plurality of MOSFET-based transistors and a plurality of resistors configured and arranged to provide a half of a supply voltage with a predetermined low output impedance while using relatively little power and circuit area.

Abstract: A common mode bias voltage generator apparatus and method includes a plurality of MOSFET-based transistors and a plurality of resistors configured and arranged to provide a half of a supply voltage with a predetermined low output impedance while using relatively little power and circuit area.

Abstract: An offset-removing gain circuit where the detected offset is independent of the gain of the circuit. The gain circuit includes a differential amplifier transfer circuit with an input and a output, an integrator connected to the output of the differential amplifier transfer circuit through a first impedance, and a second impedance connecting an output of the integrator to the input of the differential amplifier. The impedances may include resistors, capacitors or combinations thereof. The circuit may further include a switched capacitor circuit, where a plurality of capacitors are connected between input and output terminals using switches, whereby the capacitance of the switched capacitor circuit is altered by the switches to remove offset at the integrator output without changing the frequency response thereof.