Abstract: Embodiments of the present disclosure provide for improved interoperable data management between a user-accessed software application and an embedded software application. In some contexts, a user-accessed application provides both its own functionality as well as enabling access to functionality of an embedded application. The embedded application is accessed via a data-driven connection that provides several technical advantages and addresses various data interoperability and persistence problems. In some embodiments, a user-accessed application may be configured to provide functionality of multiple embedded applications consistent with the innovations herein described.

Abstract: Described herein are battery packs and electric vehicles using these packs. In some examples, a battery pack comprises two portions/covers and a set of battery modules positioned within the enclosed cavity formed by these portions. A battery pack may comprise a set of pressure-relief valves positioned in and protruding through a wall of at least one portion. Each valve can be coaxial with a corresponding gap provided between two adjacent modules. The valve is configured to provide a fluid path (to the exterior of the battery pack) when the pressure inside the pack exceeds a set threshold. In some examples, the battery pack comprises an inlet tube fluidically coupled to the inlet port of each module and an outlet tube fluidically coupled to the outlet port of each module. A set of specially configured orifices or controllable valves is positioned on the fluid path through each module.

Abstract: A method of assembling a fuel cell stack includes depositing a liquid seal material on an interconnect, pressing a fuel cell into the liquid seal material, and solidifying the liquid seal material after pressing the fuel cell into the liquid seal material. The seal material may also include a support portion or extensions which are configured to reduce an amount of compressive stress on corners of the fuel cell in the fuel cell stack.

Abstract: A rotatable ring control mechanism is mounted on a control arm of a riding mower and allows a user to control a function of the riding mower. The mechanism includes an inner support component and an outer interface ring. The inner component secures the mechanism to the control arm and includes a signal generating technology receiving a control input and generating a corresponding control signal. The outer ring rotates around the inner component and around a longitudinal axis of the control arm to provide the control input to the signal generating technology.

Abstract: Apparatus and methods are provided for distributing linear and interactive virtual reality (“VR”) video content. The VR content may be distributed by streaming over varying consumer network connections such as Wi-Fi, LTE Wireless Radio, or wired network connections. Bandwidth and latency may vary from network-user to network-user and may also vary widely during the playback of the VR content as other network users vary their bandwidth usage. Apparatus and methods are provided for ingesting, managing, composing, tracking, and experiencing VR content. Apparatus and methods are provided for reducing bandwidth and computational overhead associated with streaming VR content to a viewing device.

Abstract: A memory system includes a sense amplifier electrically coupled to a first bitline and a second bitline associated with a column of a memory array, a bl transistor electrically coupled to the first bitline, wherein the bl transistor is configured to receive as input a first electrical signal from the first bitline, and a blb transistor electrically coupled to the second bitline, wherein the blb transistor is configured to receive as input a second electrical signal from the second bitline, wherein an output of the bl transistor and an output of the blb transistor are electrically coupled together as a common output, and wherein the sense amplifier is configured to receive as an input the common output of the bl transistor and the blb transistor.

Abstract: Providing efficient handling of memory array failures in processor-based systems is disclosed. In this regard, in one aspect, a memory controller of a processor-based device is configured to detect a defect within a memory element of a plurality of memory elements of a memory array. In response, a disable register of one or more disable registers is set to correspond to the memory element to indicate that the memory element is disabled. The memory controller receives a memory access request to a memory address corresponding to the memory element, and determines, based on one or more disable registers, whether the memory element is disabled. If so, the memory controller disallows the memory access request. Some aspects may provide that the memory controller, in response to detecting the defect, provides a failure indication to an executing process, and subsequently receives, from the executing process, a request to set the disable register.

Abstract: Apparatus and methods are provided for distributing linear and interactive virtual reality (“VR”) video content. The VR content may be distributed by streaming over varying consumer network connections such as Wi-Fi, LTE Wireless Radio, or wired network connections. Bandwidth and latency may vary from network-user to network-user and may also vary widely during the playback of the VR content as other network users vary their bandwidth usage. Apparatus and methods are provided for ingesting, managing, composing, tracking, and experiencing VR content. Apparatus and methods are provided for reducing bandwidth and computational overhead associated with streaming VR content to a viewing device.

Abstract: Disclosed is a memory system comprising a sense amplifier electrically coupled to a first bitline and a second bitline associated with a column of a memory array, a bl transistor electrically coupled to the first bitline, wherein the bl transistor is configured to receive as input a first electrical signal from the first bitline, and a blb transistor electrically coupled to the second bitline, wherein the blb transistor is configured to receive as input a second electrical signal from the second bitline, wherein an output of the bl transistor and an output of the blb transistor are electrically coupled together as a common output, and wherein the sense amplifier is configured to receive as an input the common output of the bl transistor and the blb transistor.

Abstract: Cache memory clock generation circuits for reducing power consumption and read errors in cache memory are provided. In one aspect, a cache memory clock generation circuit employs detector circuit configured to receive a way address and generate a one way hit signal indicating if cache read request results in a single way hit. Clock and enable circuit is configured to generate a cache clock signal in response to a system clock signal and a cache enable signal, and generate a cache read enable signal in response to the cache clock signal and a read enable signal. Gating circuit is configured to generate a read clock signal in response to one way hit signal, cache clock signal, and cache read enable signal. Sense amplifier clock generation circuit is configured to generate sense amplifier clock signal in response to the read clock signal having a defined pulse width.

Abstract: Providing efficient handling of memory array failures in processor-based systems is disclosed. In this regard, in one aspect, a memory controller of a processor-based device is configured to detect a defect within a memory element of a plurality of memory elements of a memory array. In response, a disable register of one or more disable registers is set to correspond to the memory element to indicate that the memory element is disabled. The memory controller receives a memory access request to a memory address corresponding to the memory element, and determines, based on one or more disable registers, whether the memory element is disabled. If so, the memory controller disallows the memory access request. Some aspects may provide that the memory controller, in response to detecting the defect, provides a failure indication to an executing process, and subsequently receives, from the executing process, a request to set the disable register.

Abstract: Cache memory clock generation circuits for reducing power consumption and read errors in cache memory are provided. In one aspect, a cache memory clock generation circuit employs detector circuit configured to receive a way address and generate a one way hit signal indicating if cache read request results in a single way hit. Clock and enable circuit is configured to generate a cache clock signal in response to a system clock signal and a cache enable signal, and generate a cache read enable signal in response to the cache clock signal and a read enable signal. Gating circuit is configured to generate a read clock signal in response to one way hit signal, cache clock signal, and cache read enable signal. Sense amplifier clock generation circuit is configured to generate sense amplifier clock signal in response to the read clock signal having a defined pulse width.

Abstract: Apparatus and methods are provided for distributing linear and interactive virtual reality (“VR”) video content. The VR content may be distributed by streaming over varying consumer network connections such as Wi-Fi, LTE Wireless Radio, or wired network connections. Bandwidth and latency may vary from network-user to network-user and may also vary widely during the playback of the VR content as other network users vary their bandwidth usage. Apparatus and methods are provided for ingesting, managing, composing, tracking, and experiencing VR content. Apparatus and methods are provided for reducing bandwidth and computational overhead associated with streaming VR content to a viewing device.

Abstract: The search key and key fields of a CAM in a cache are encoded with a Hamming distance of at least two to increase the speed of the CAM by ensuring each mismatching match line is discharged by at least two transistors in parallel. Where the cache is physically tagged, the search key is a physical address. The page address portion of the physical address is encoded prior to being stored in a TLB. The page offset bits are encoded in parallel with the TLB access, and concatenated with the encoded TLB entry. If a page address addresses a large memory page size, a plurality of corresponding sub-page addresses may be generated, each addressing a smaller page size. These sub-page addresses may be encoded and stored in a micro TLB. The encoded key and key field are tolerant of single-bit soft errors.

Abstract: A CAM bank is functionally divided into two or more sub-banks, without replication CAM driver circuits, by disabling all match line discharge circuits in the bank, and selectively enabling the discharge circuits in comprising sub-banks. At least one selectively actuated switching circuit is interposed between the virtual ground node of each discharging comparator in the discharge circuit of a sub-bank and circuit ground. When the switching circuit is in a non-conductive state, the virtual ground node is maintained at a voltage level sufficiently above circuit ground to preclude discharging a connected match line within the CAM access time. When the switching circuit is placed in a conductive state, the virtual ground node is pulled to circuit ground and the connected match line may be discharged by a miscompare. Control signals, which may be decode from address bits, are distributed to the switching circuits to defined the CAM sub-banks.

Abstract: This invention reduces power consumed during CAM search operations in a CAM/RAM structure utilizing a segmented match line structure. This device is useful when it is known that a portion or portions of the compare data inputs vary infrequently. The apparatus sometimes may be referred to as local match line hold latch, and is a device that stores the value of a local match line comparison result the first time that a search operation occurs, and will stay at that value until the value of the compare data in of the local match line changes.

Abstract: The present invention relates to a head restraint assembly providing four-way adjustment and having dual positive stops as well as a single ergonomic control. The present invention includes a frame and a housing that engages a portion of the frame. The present invention further includes a cam assembly disposed within the housing to provide fore/aft adjustment of the housing relative to the frame. The cam assembly includes a camshaft and at least two drum assemblies supported by the camshaft. The cam assembly further includes a contact plate extending parallel to the camshaft to releasably engage the drum assemblies. The camshaft is connected to the contact plate to provide releasable engagement between the contact plate and the drum assemblies. The present invention further includes a control member to engage the cam assembly and provide for fore/aft and vertical adjustment in response to user input.

Abstract: The present invention relates to a head restraint assembly providing four-way adjustment and having dual positive stops as well as a single ergonomic control. The present invention includes a frame and a housing that engages a portion of the frame. The present invention further includes a cam assembly disposed within the housing to provide fore/aft adjustment of the housing relative to the frame. The cam assembly includes a camshaft and at least two drum assemblies supported by the camshaft. The cam assembly further includes a contact plate extending parallel to the camshaft to releasably engage the drum assemblies. The camshaft is connected to the contact plate to provide releasable engagement between the contact plate and the drum assemblies. The present invention further includes a control member to engage the cam assembly and provide for fore/aft and vertical adjustment in response to user input.