Patents by Inventor Michael Phaneuf

Michael Phaneuf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6684379
    Abstract: A design analysis workstation for performing design analysis of integrated circuits provides facilities for extracting design and layout information from digital image-mosaics captured during deconstruction of an integrated circuit. Each image-mosaic is displayed in at least one mosaic-view as a background image that is overlaid with at least one annotation overlay. An engineer analyst creates annotation objects on the annotation overlay based on information inferred concurrently from one or more image-mosaics. Concurrent display of a plurality of image-mosaics facilitates the understanding of interrelations between components on different layers. The design analysis workstation displays a plurality of cursors in respective views of mosaic-images, the cursors having lock-step motion to facilitate comprehension of the alignment of features on different concurrently displayed image-mosaics.
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: January 27, 2004
    Assignee: Chipworks
    Inventors: David F. Skoll, Terry Ludlow, Julia Elvidge, Michael Phaneuf
  • Patent number: 6641705
    Abstract: A charged particle beam uniformly removes material, particularly crystalline material, from an area of a target by compensating for or altering the crystal orientation or structure of the material to be removed. The invention is particularly suited for FIB micromachining of copper-based crystalline structures. Uniformity of material removal can be improved, for example, by passing incoming ions through a sacrificial layer formed on the surface of the material to be removed. The sacrificial layer is removed along with the material being milled. Uniformity of removal can also be improved by changing the morphology of the material to be removed, for example, by disrupting its crystal structure or by altering its topography.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: November 4, 2003
    Assignee: FEI Company
    Inventors: Michael Phaneuf, Jian Li, Richard F. Shuman, Kathryn Noll, J. David Casey, Jr.
  • Patent number: 6453063
    Abstract: A method of imaging an integrated circuit using a focused ion beam system is presented. According to the method an integrated circuit is imaged in plan-view using a focused ion beam system. Circuit information is then extracted absent processing. In another embodiment, a method and system for imaging an entire IC automatically without removing the IC from the imaging system and requiring minimal operator intervention is presented. The method employs a focused ion beam system to image an exposed layer of an integrated circuit and then to etch a portion of the exposed layer in situ. Imaging and etching are repeated until substantially the entire integrated circuit is imaged. A processor is used to assemble the layers into a three-dimensional topography of the integrated circuit. Because of known relationships between layers, the mosaicing is facilitated and the final topography is more reliable than those produced by currently known computer implemented methods.
    Type: Grant
    Filed: January 28, 1999
    Date of Patent: September 17, 2002
    Assignee: Chipworks
    Inventors: Michael Phaneuf, Dick James, Julia Elvidge, Pierrette Breton, Terry Ludlow, David Skoll, Bryan Socransky, Louise Weaver, Ray Haythornthwaite
  • Publication number: 20020046386
    Abstract: A design analysis workstation for performing design analysis of integrated circuits provides facilities for extracting design and layout information from digital image-mosaics captured during deconstruction of an integrated circuit. Each image-mosaic is displayed in at least one mosaic-view as a background image that is overlaid with at least one annotation overlay. An engineer analyst creates annotation objects on the annotation overlay based on information inferred concurrently from one or more image-mosaics. Concurrent display of a plurality of image-mosaics facilitates the understanding of interrelations between components on different layers. The design analysis workstation displays a plurality of cursors in respective views of mosaic-images, the cursors having lock-step motion to facilitate comprehension of the alignment of features on different concurrently displayed image-mosaics.
    Type: Application
    Filed: August 13, 2001
    Publication date: April 18, 2002
    Applicant: Chipworks
    Inventors: David F. Skoll, Terry Ludlow, Julia Elvidge, Michael Phaneuf
  • Publication number: 20010053605
    Abstract: A charged particle beam uniformly removes material, particularly crystalline material, from an area of a target by compensating for or altering the crystal orientation or structure of the material to be removed. The invention is particularly suited for FIB micromachining of copper-based crystalline structures. Uniformity of material removal can be improved, for example, by passing incoming ions through a sacrificial layer formed on the surface of the material to be removed. The sacrificial layer is removed along with the material being milled. Uniformity of removal can also be improved by changing the morphology of the material to be removed, for example, by disrupting its crystal structure or by altering its topography.
    Type: Application
    Filed: March 27, 2001
    Publication date: December 20, 2001
    Inventors: Michael Phaneuf, Jian Li, Richard F. Shuman, Kathryn Noll, J. David Casey
  • Patent number: 6288393
    Abstract: A method of analysing integrated circuits is provided. The method provides for scanning the integrated circuit with a beam in order to image an upper layer of the integrated circuit and performing chemical analysis on the upper layer of the integrated circuit. The chemical information and the imaging information are correlated and used to reverse engineer the integrated circuit.
    Type: Grant
    Filed: January 28, 1999
    Date of Patent: September 11, 2001
    Assignee: Chipworks
    Inventors: Michael Phaneuf, Dick James, Pierrette Breton, Julia Elvidge, Ray Haythornthwaite