Abstract: A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.

Abstract: A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.

Abstract: A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.

Abstract: A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.

Abstract: A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.

Abstract: A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.

Abstract: A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.

Abstract: A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.

Abstract: A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.

Abstract: A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.

Abstract: A tile of an FPGA fuses memory and arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased. The arithmetic unit accesses inputs from a combination of: the switch fabric, the memory circuit, a second memory circuit of the tile, and a cascade input. In some example embodiments, the routing of the connections on the tile is based on post-fabrication configuration. In one configuration, all connections are used by the memory circuit, allowing for higher bandwidth in writing or reading the memory. In another configuration, all connections are used by the arithmetic circuit.

Abstract: A tile of an FPGA fuses memory and arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased. The arithmetic unit accesses inputs from a combination of: the switch fabric, the memory circuit, a second memory circuit of the tile, and a cascade input. In some example embodiments, the routing of the connections on the tile is based on post-fabrication configuration. In one configuration, all connections are used by the memory circuit, allowing for higher bandwidth in writing or reading the memory. In another configuration, all connections are used by the arithmetic circuit.

Abstract: The present invention relates to wireless communication networks particularly for indoor deployment, in which there typically directly exists a rapidly changing multipath propagation environment with limited opportunities for line of sight wireless communication. The present invention provides A wireless communications network for communicating with a mobile terminal; comprising: a number of repeater points each comprising means for communicating with the mobile terminal; an access point comprising means for communicating with the repeater points; the repeater points further comprising means for relaying signals between the terminal and the access point; means for determining a quality measure of signals sent by the terminal and received by the access point via the repeater points; means for selecting one or more repeater points to relay transmission signals from the access point to the terminal, said selection based on said quality measures of the terminal signals received by the access point.

Abstract: Spread spectrum receiver architectures and methods are described for reducing interference, particularly the interference observed at a user-end terminal in a W-CDMA 3G mobile communications system. Interpath interference which arises due to non-zero cross and auto correlation of more than one spreading code is suppressed by estimating a transmitted signal stream, or a plurality of such signal streams in the case of a plurality of multipath components, respreading this estimated signal and subtracting non-orthogonal interference contributions from a received signal. The techniques provide an improved bit error rate or equivalently, enhanced capacity for a digital mobile communications network.

Abstract: Independent radio communication devices can share network information directly with each other in the local area using an independent wireless link. This network information encompasses synchronisation information, interference, network configuration, neighbour cell list, paging requests, etc., and can be relevant to multiple networks, frequency carriers and/or air interface modes. Sharing the information reduces the processing requirement, the power consumption, and the bandwidth consumption of devices.

Abstract: The invention relates to communication between terminals. Where communication is over an ideal channel then a high throughput modulation scheme can be used. Where the terminals suffer interference or noise, transmission can be modified to a more robust modulation scheme. The modulation scheme for a signal to be transmitted from the terminal is normally selected based up measurements made on a signal received by the terminal. However, the uplink and downlink between two terminals may not be experiencing the same interference and noise. For example, an interfering source may affect one terminal more than another. Under these circumstances, the terminal will not get a good picture of the status of the channel or link over which it is about to transmit. Therefore, the invention provides a system where quality information is passed from the terminal receiving a signal to the terminal which sent the signal to help to determine the most appropriate modulation scheme.

Abstract: An equalizer for a digital communications system includes a first buffer to store received data prior to equalisation; a second buffer to store error-checked received data; a channel estimator coupled to the first and second buffers to determine a channel estimate using the received data from the first buffer and the error-checked data from the second buffer; and a control unit coupled to the channel estimator to update a channel estimate for use by the equalizer in equalizing the received data. The control unit performs the updating conditional upon a difference between the channel estimate and a previous channel estimate used for equalizing the received data. A look-up table is coupled to the control unit and a calculating device is coupled to the look-up table to calculate and store, in the look-up table, data obtained by applying the channel estimate to a sequence of symbols.

Abstract: A multicode receiver for receiving data carried by a plurality of spread spectrum signals having a corresponding plurality of spreading codes, the spreading codes being substantially mutually orthogonal, the receiver having intercode interference suppression, the receiver including a multicode spread spectrum receiver to provide a set of data estimates having a plurality of estimates of data carried by the plurality of spread spectrum signals, one estimate for each spread spectrum signal, a plurality of respreaders to respread the plurality of data estimates, a plurality of interference suppressers, at least one for each of the plurality of spreading codes, each at least one interference suppresser for each code being configured to suppress respread data estimates for the spread spectrum signals of the other codes, from a received signal, a plurality of rake fingers each having the plurality of interference suppressers, and a plurality of rake combiners, one for each of the plurality of spreading codes.

Abstract: The present invention relates to wireless communication networks particularly for indoor deployment, in which there typically directly exists a rapidly changing multipath propagation environment with limited opportunities for line of sight wireless communication. The present invention provides A wireless communications network for communicating with a mobile terminal; comprising: a number of repeater points each comprising means for communicating with the mobile terminal; an access point comprising means for communicating with the repeater points; the repeater points further comprising means for relaying signals between the terminal and the access point; means for determining a quality measure of signals sent by the terminal and received by the access point via the repeater points; means for selecting one or more repeater points to relay transmission signals from the access point to the terminal, said selection based on said quality measures of the terminal signals received by the access point.

Abstract: This invention is generally concerned with apparatus and methods for signal processing, and more particularly with improved techniques for diversity reception in communication systems.