Abstract: A glitch suppression circuit has a read pointer and a write pointer that track memory locations. A comparator compares the read pointer and the write pointer and provides a compare signal indicative of a particular memory condition. The glitch suppression circuit includes an offset read pointer and an offset write pointer that track memory locations. An offset comparator compares the read pointer and the write pointer and provides an offset compare signal indicative of the particular memory condition. A timing signal controls a multiplexer for selecting either the compare signal or the offset compare signal and sets a logic flag. The setting of the logic flag may be synchronized to a timing signal.

Abstract: A glitch suppression circuit has a read pointer and a write pointer that track memory locations. A comparator compares the read pointer and the write pointer and provides a compare signal indicative of a particular memory condition. The glitch suppression circuit includes an offset read pointer and an offset write pointer that track memory locations. An offset comparator compares the read pointer and the write pointer and provides an offset compare signal indicative of the particular memory condition. A timing signal controls a multiplexer for selecting either the compare signal or the offset compare signal and sets a logic flag. The setting of the logic flag may be synchronized to a timing signal.