Abstract: Basic cells (GZ) that are composed of at least three p-channel transistors (TP) and of three n-channel transistors (TN) are employed for constructing a read-only memory. Only the outwardly disposed transistors (TP1, TP2) or, respectively, TN1, TN2) are employed for storing the information, whereas the inwardly disposed transistors (TN3, TP3) are not used. An information is stored in that the gate electrode (G) of one transistor (TP, TN) is connected to a word line (W), the drain electrode is connected to a bit line and the source electrode is connected to a fixed supply voltage (VDD, VSS) or is not connected thereto. The layout of the basic cell (GZ) is executed such that the gate terminals ensue in the inner region of the basic cell and the word lines (W) and bit lines (B) are conducted over the basic cell perpendicularly relative to one another. Read-only memories of arbitrary size can be realized by joining such basic cells in rows and columns.

Abstract: A data processing system having an arithmetic unit is designed for a multiplication of n-place numbers in 2's complement according to the Booth algorithm, and for division of unsigned numerals. A 2n-stage shift register is connected over a logical control circuit to the operation code inputs of an ALU. The control circuit automatically forms instruction code signals to the ALU as a function of informational bits derived from the shift register, whereas other operation code input signals are directly connected to the operation code inputs. The control circuit is a sequential circuit having a multiplexer for the selective through-connection of the multiplication code signals, the division code signals, or other operation code signals to the operation code inputs of the ALU.

Abstract: In order to permit good test results in the voltage measurement of buried test subjects, an arrangement is provided having a particle beam probe for voltage measurement at a test subject which is spatially separated from a surface by a solid state substance. The solid state substance provides mobile charges disposed in insulated fashion between said test subject and the particle beam probe. A charge separation due to the influence of the test subject potential is produced in the solid state substance so that a potential on the surface of the solid state substance immediately adjacent to the particle beam probe becomes proportional to the potential on the test subject.

Abstract: A system is disclosed for coupling electrically isolated circuits in a monolithic integrated circuit. A signal coupler is integrated on a chip together with a primary circuit and a secondary circuit which is to be coupled to the primary circuit. The signal coupler comprises an integrated coupling capacitor which consists of a coplanar conductor path arrangement embedded into a passivation layer, the passivation layer being applied to an insulating substrate, preferably sapphire.

Abstract: An integrated current supply circuit is disclosed which utilizes a sub-circuit having a lambda-like current-voltage curve. Such a sub-circuit comprises a first field effect transistor whose source-drain path is connected to a series circuit formed from a load element and a second field effect transistor. The gate of the first field effect transistor is connected to the connection point of the load element and the second field effect transistor. A gate of the second FET leads either directly or via a voltage divider to the drain-side terminal of the series circuit. A capacitor is provided which is connected across output terminals of the circuit. The series circuit of the lambda sub-circuit is connected in parallel with input terminals, and the first FET connects between one of the input terminals and one of the output terminals.

Abstract: Two semiconductor chips having complementary MOS circuits are interconnected by means of an output stage provided on the first chip and an input stage provided on the second chip. The connection is a high-speed connection despite the relatively high internal impedance of the MOS transistors. The output stage incorporates MOS transistors for transforming the signal level to a relatively low level, and the input stage incorporates MOS transistors interconnected as a pulsed trigger or amplifier for restoring the low signal to a relatively high level for connection to other MOS circuits.

Abstract: A static semiconductor storage element includes a flip-flop formed of a pair of complementary field effect transistors which are cross coupled without intersection to form a bistable circuit. One node of the flip-flop is connected to a terminal which is employed for both reading and writing functions. The flip-flop is set or reset by connection of an appropriate voltage to the node, and nondestructive read out is carried out by sensing the voltage level of the node.