Abstract: An automated order fulfillment system and mobile robot are disclosed, where the mobile robot includes a compliant drive for moving between levels of a multilevel storage structure.

Abstract: An automated order fulfillment system and mobile robot are disclosed, where the mobile robot includes a compliant drive for moving between levels of a multilevel storage structure. In one example, the compliant drive comprises a drive shaft having splines configured to provide rotational play that prevents jamming of a vertical drive gear on the end of the shaft with a rack in a vertical track.

Abstract: A thin film-retaining washer with custom geometry that may further provide for a simple press-on installation while maintaining retention of fasteners during assembly, shipping, handling, and/or use of associated systems. The present retaining hardware is easily manufactured from sheet or film materials with minimal post-processing and may be scaled and optimized for use with multiple size and style of fasteners. Further, the thickness profile of the thin film retaining hardware facilitates lobe spring deflection to further provide secure retention of the associated fasteners.

Abstract: Provided herein are energy storage devices. In some cases, the energy storage devices are capable of being transported on a vehicle and storing a large amount of energy. An energy storage device is provided comprising at least one liquid metal electrode, an energy storage capacity of at least about 1 MWh and a response time less than or equal to about 100 milliseconds (ms).

Abstract: Disclosed herein are differential amplifiers for improved slew performance. In some embodiments, a differential amplifier may receive positive and negative input signals at first and second transistor branches, respectively; provide a dynamic bias current to the first and second transistor branches, responsive to the positive and negative input signals; and provide positive and negative output signals at the second and first transistor branches, respectively.

Abstract: Disclosed herein are differential amplifiers for improved slew performance. In some embodiments, a differential amplifier may receive positive and negative input signals at first and second transistor branches, respectively; provide a dynamic bias current to the first and second transistor branches, responsive to the positive and negative input signals; and provide positive and negative output signals at the second and first transistor branches, respectively.

Abstract: In one aspect, a current source is provided to limit noise and offset. In one embodiment, a source transistor is provided, with current sourced at the drain. A feedback network runs from the source node to the gate. The feedback network produces voltage gain by a transconductance, such as a transistor. Appropriate capacitors are also provided, and two pairs of switches are disposed to provide offset cancellation by toggling between gain and clamp modes in the switched capacitor architecture.

Abstract: In one example embodiment, a current source is provided to limit noise and offset. In one embodiment, a source transistor is provided, with current sourced at the drain. A feedback network runs from the source node to the gate. The feedback network produces voltage gain by a transconductance, such as a transistor. Appropriate capacitors are also provided, and two pairs of switches are disposed to provide offset cancellation by toggling between gain and clamp modes in the switched capacitor architecture.

Abstract: A transmission system may include an oscillator, a serializer, and a driver. The oscillator may generate at least two clock signals. The serializer may modulate a plurality of data streams based upon the at least two clock signals and a plurality of channels of data. The driver may receive and combine the plurality of data streams into a single output data stream, wherein the single output data stream has a clock frequency higher than frequency of each of the at least two clock signals.

Abstract: A system and method are described herein that provide for the calibration of the offset of a comparator on a per-comparator basis. An injection is made to the comparator at determined injection points using a low-power DAC, to calibrate the offset of the comparator. The DAC can be selectively controlled by a digital codeword that is generated based on an output of the comparator and the comparator's offset. Further embodiments of the invention present a system and method for calibrating the offset of a comparator of a flash ADC in each stage of a pipeline ADC. The system and method may provide for the calibration in a manner without affecting the speed of the pipeline ADC or adding significant power to the pipeline ADC.

Abstract: A multiplying analog-to-digital converter (“MDAC”) that reduces the power consumption of the MDAC by at least 2.3 times by improving the feedback factor. The amplifier may include a feed forward approach in which the input capacitor (also referred to as “sampling capacitor”) is buffered by a common gate amplifier to improve bandwidth by removing input and parasitic capacitance terms from the global feedback loss. THe amplifier may also use an alternate form of local compensation, for example, cascode compensation. The amplifier may also further include an alternate way to reduce parasitic capacitance with a buffer.

Abstract: A system provides for a serial transmitter with multiplexing and driving functionality that is combined into a single stage to increase the overall speed of the serial transmitter. The single stage includes a dynamic impedance that is configured in parallel with a multiplexing driver to reduce the input capacitance and set the correct output impedance. The single stage can be implemented as a stacked or cross-coupled XOR logic circuit or a stacked or cross-coupled multiplexer (“mux”) as the multiplexing driver. In an embodiment where a mux is used as the multiplexing driver, a clock can be injected into the mux driver to overcome inter-symbol interference.

Abstract: A system and method are described herein that provide for the calibration of the offset of a comparator on a per-comparator basis. An injection is made to the comparator at determined injection points using a low-power DAC, to calibrate the offset of the comparator. The DAC can be selectively controlled by a digital codeword that is generated based on an output of the comparator and the comparator's offset. Further embodiments of the invention present a system and method for calibrating the offset of a comparator of a flash ADC in each stage of a pipeline ADC. The system and method may provide for the calibration in a manner without affecting the speed of the pipeline ADC or adding significant power to the pipeline ADC.

Abstract: Data transmitter embodiments are provided which are particularly useful as interface devices for accurate and reliable transmittal of data from high-speed data system devices such as analog-to-digital converters. Transmitter embodiments have been found to provide excellent fidelity of data transfer at high data rates (e.g., 4 gigabits/second) while consuming only a portion of the power of many conventional transmitters and requiring only a portion of the layout area of these transmitters. Transmitter embodiments provide effective control of transmitter parameters such as matched impedances, data symmetry, common-mode level, data eye and current drain.

Abstract: Signal converter systems are provided which reduce degradation of system bit error rate that is caused by metastable conversion errors which generally occur when analog input signals are near reference thresholds Vth of system comparators. When operating correctly, the comparators generate a corresponding converter code when the input signals cross the threshold. Metastability, however, may cause the comparators to fail to generate the corresponding converter code. In system embodiments, logic is provided to sense the absence of comparator decisions at the end of a predetermined decision period. In response to this absence, the system is configured to substitute the corresponding converter code. In another embodiment, the system is configured to substitute the corresponding converter code when it lies outside a predetermined digital code window.

Abstract: Signal converter systems are provided which reduce degradation of system bit error rate that is caused by metastable conversion errors which generally occur when analog input signals are near reference thresholds Vth of system comparators. When operating correctly, the comparators generate a corresponding converter code when the input signals cross the threshold. Metastability, however, may cause the comparators to fail to generate the corresponding converter code. In system embodiments, logic is provided to sense the absence of comparator decisions at the end of a predetermined decision period. In response to this absence, the system is configured to substitute the corresponding converter code. In another embodiment, the system is configured to substitute the corresponding converter code when it lies outside a predetermined digital code window.

Abstract: Data transmitter embodiments are provided which are particularly useful as interface devices for accurate and reliable transmittal of data from high-speed data system devices such as analog-to-digital converters. Transmitter embodiments have been found to provide excellent fidelity of data transfer at high data rates (e.g., 4 gigabits/second) while consuming only a portion of the power of many conventional transmitters and requiring only a portion of the layout area of these transmitters. Transmitter embodiments provide effective control of transmitter parameters such as matched impedances, data symmetry, common-mode level, data eye and current drain.

Abstract: Control structures are provided to accurately maintain amplifier common-mode levels at the predetermined level of a common-mode reference voltage Vcm. The disclosed control structures provide amplifier feedback along a first feedback path that is configured to provide high gain and low bandwidth to closely maintain amplifier common-mode level at the predetermined level of a common-mode reference voltage Vcm. They also provide amplifier feedback along a second feedback path that is configured to provide wide bandwidth to substantially reduce perturbations of the common-mode level that would have otherwise been induced by input signal transients. In an important amplifier feature, these controls are obtained without use of structures (e.g., capacitors and switching transistors) that use substantial current which reduces amplifier efficiency.

Abstract: A separator placed in a mist collection system prior to a final air cleaning stage, and is configured to remove a substantial portion of the mist from the air. The separator includes stationary vanes in a cylindrical housing to establish a cyclonic flow therethrough, an annular flow restriction collar to establish a liquid collection area at the downstream end of the housing, a drain for discharge of the liquid from the collection area, and a flow interrupter to direct the swirling liquid into the drain.

Abstract: Current-control reference systems are provided in which stabliity is realized with sensors that shift clamp windows in response to a reference's current-control signal to thereby maintain feedback control in the reference under steady-state and transient operating conditions.