Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

Abstract: A series-parallel scan, IR, focal plane array which uses small InSb CID mles. The CID is used to premultiplex photocurrent through a preamplifier before the photosignal is introduced into a Si CCD TDI signal processor.