Patents by Inventor Michael Röhner

Michael Röhner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10242922
    Abstract: A semiconductor wafer includes dielectric regions of different thicknesses, some of the dielectric regions being thinner and other ones of the dielectric regions being thicker. The semiconductor wafer further includes a stress circuit operable to stress at least one of the dielectric regions internally within the semiconductor wafer for assessing dielectric reliability. A corresponding method of internally assessing dielectric reliability of a semiconductor technology is also provided.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: March 26, 2019
    Assignee: Infineon Technologies AG
    Inventors: Michael Röhner, Stefano Aresu, Marco Faricelli
  • Publication number: 20150194358
    Abstract: A semiconductor wafer includes dielectric regions of different thicknesses, some of the dielectric regions being thinner and other ones of the dielectric regions being thicker. The semiconductor wafer further includes a stress circuit operable to stress at least one of the dielectric regions internally within the semiconductor wafer for assessing dielectric reliability. A corresponding method of internally assessing dielectric reliability of a semiconductor technology is also provided.
    Type: Application
    Filed: January 9, 2014
    Publication date: July 9, 2015
    Inventors: Michael Röhner, Stefano Aresu, Marco Faricelli
  • Patent number: 6858492
    Abstract: Capacitor devices are formed in an essentially vertically extending fashion in order to achieve an essentially three-dimensional configuration or a configuration extending into the third dimension. A contacting of plug regions is performed after producing the capacitor devices. Such capacitor devices provide an increased integration density in a semiconductor memory device.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: February 22, 2005
    Assignee: Infineon Technologies AG
    Inventors: Rainer Bruchhaus, Gerhard Enders, Walter Hartner, Matthias Krönke, Thomas Mikolajick, Nicolas Nagel, Michael Röhner
  • Patent number: 6818503
    Abstract: A method of fabricating semiconductor memory devices is simplified by providing at least some plug regions, which are provided for contacting storage capacitor devices of a capacitor configuration, such that the plug regions have in each case a region that is elevated above the surface region of a passivation region.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: November 16, 2004
    Assignee: Infineon Technologies AG
    Inventors: Rainer Bruchhaus, Gerhard Enders, Walter Hartner, Igor Kasko, Matthias Krönke, Thomas Mikolajick, Nicolas Nagel, Michael Röhner, Volker Weinrich
  • Patent number: 6773986
    Abstract: To achieve a highest possible integration density in a semiconductor memory device having storage capacitors as storage elements, the method according to the invention forms the capacitor devices in substantially vertically extending fashion, to, as a result, achieve a substantially three-dimensional configuration and an configuration extending into the third dimension for the capacitor devices, a contact connection of the storage capacitors being formed after the production of the storage capacitors.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: August 10, 2004
    Assignee: Infineon Technologies AG
    Inventors: Rainer Bruchhaus, Gerhard Enders, Walter Hartner, Matthias Krönke, Thomas Mikolajick, Nicolas Nagel, Michael Röhner
  • Patent number: 6704219
    Abstract: To manufacture FeRAM memories in a particularly space-saving fashion and, thus, increase the storage density, a manufacturing method forms at least some of the multiplicity of capacitor devices used as storage elements with a multiplicity of individual capacitors that are connected in parallel with one another. The individual capacitors have ferroelectric or paraelectric dielectric regions with different coercitive voltages such that there is a resulting multiplicity of storage states for each of the individual capacitors.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: March 9, 2004
    Assignee: Infineon Technologies AG
    Inventors: Rainer Bruchhaus, Gerhard Enders, Walter Hartner, Matthias Krönke, Thomas Mikolajick, Nicolas Nagel, Michael Röhner
  • Publication number: 20030129796
    Abstract: Capacitor devices are formed in an essentially vertically extending fashion in order to achieve an essentially three-dimensional configuration or a configuration extending into the third dimension. A contacting of plug regions is performed after producing the capacitor devices. Such capacitor devices provide an increased integration density in a semiconductor memory device.
    Type: Application
    Filed: July 1, 2002
    Publication date: July 10, 2003
    Inventors: Rainer Bruchhaus, Gerhard Enders, Walter Hartner, Matthias Kronke, Thomas Mikolajick, Nicolas Nagel, Michael Rohner
  • Publication number: 20030060002
    Abstract: A method of fabricating semiconductor memory devices is simplified by providing at least some plug regions, which are provided for contacting storage capacitor devices of a capacitor configuration, such that the plug regions have in each case a region that is elevated above the surface region of a passivation region.
    Type: Application
    Filed: July 1, 2002
    Publication date: March 27, 2003
    Inventors: Rainer Bruchhaus, Gerhard Enders, Walter Hartner, Igor Kasko, Matthias Kronke, Thomas Mikolajick, Nicolas Nagel, Michael Rohner, Volker Weinrich
  • Publication number: 20030058700
    Abstract: To achieve a highest possible integration density in a semiconductor memory device having storage capacitors as storage elements, the method according to the invention forms the capacitor devices in substantially vertically extending fashion, to, as a result, achieve a substantially three-dimensional configuration and an configuration extending into the third dimension for the capacitor devices, a contact connection of the storage capacitors being formed after the production of the storage capacitors.
    Type: Application
    Filed: July 1, 2002
    Publication date: March 27, 2003
    Inventors: Rainer Bruchhaus, Gerhard Enders, Walter Hartner, Matthias Kronke, Thomas Mikolajick, Nicolas Nagel, Michael Rohner
  • Publication number: 20030053346
    Abstract: To manufacture FeRAM memories in a particularly space-saving fashion and, thus, increase the storage density, a manufacturing method forms at least some of the multiplicity of capacitor devices used as storage elements with a multiplicity of individual capacitors that are connected in parallel with one another. The individual capacitors have ferroelectric or paraelectric dielectric regions with different coercitive voltages such that there is a resulting multiplicity of storage states for each of the individual capacitors.
    Type: Application
    Filed: July 1, 2002
    Publication date: March 20, 2003
    Inventors: Rainer Bruchhaus, Gerhard Enders, Walter Hartner, Matthias Kronke, Thomas Mikolajick, Nicolas Nagel, Michael Rohner