Patents by Inventor Michael R. Hsing
Michael R. Hsing has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8917076Abstract: An off-line regulator has a rectification circuit configured to rectify an AC line voltage into a rectified line voltage, a pass device coupled between the rectified line voltage and a first capacitor, and a converter. The pass device is configured to be turned ON or OFF according to a comparison signal indicating whether the rectified line voltage is over a threshold voltage. The first capacitor delivers an interim voltage into the converter which supplies power to a load. Wherein a second capacitor coupled across a driver which driving the pass device is charged by the first capacitor when the comparison signal is at a first state, and the driver is boosted when the comparison signal is at a second state.Type: GrantFiled: August 10, 2012Date of Patent: December 23, 2014Assignee: Monolithic Power Systems, Inc.Inventors: Michael R. Hsing, Eric Yang, Zheng Luo, Ken Yi, Yiqing Jin, Yuancheng Ren
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Patent number: 8598637Abstract: In one embodiment, a junction field effect transistor having a substrate, wherein formed on the substrate is a graded n-doped region having a high doping concentration in an inner region and a low doping concentration in an outer region, with a p-doped buried region adjacent to the graded n-doped region near the outer region, and a spiral resistor connected to the graded n-doped region at its inner region and at its outer region. An ohmic contact at the inner region provides the drain, an ohmic contact at the outer region provides the source, and an ohmic contact at the substrate provides the gate.Type: GrantFiled: September 18, 2009Date of Patent: December 3, 2013Assignee: Monolithic Power Systems, Inc.Inventors: Michael R. Hsing, Martin E. Garnett, Ognjen Milic
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Patent number: 8525260Abstract: RESURF effect devices with both relatively deep trenches and relatively deep implants are described herein. Also, methods of fabricating such devices are described herein. A RESURF effect device may include alternating regions of first and second conductivity types where each of the second regions includes an implant region formed into a trench region of the second region.Type: GrantFiled: March 19, 2010Date of Patent: September 3, 2013Assignee: Monolithic Power Systems, Inc.Inventors: Tiesheng Li, Michael R. Hsing, Deming Xiao
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Patent number: 8400778Abstract: A multi-phase voltage regulator is disclosed where each phase is comprised of an array of high and low side transistors that are integrated onto a single substrate. Further, a system of mounting the voltage regulator onto a flip chip and lead frame is disclosed wherein the source and drain lines form an interdigital pattern.Type: GrantFiled: February 2, 2010Date of Patent: March 19, 2013Assignee: Monolithic Power Systems, Inc.Inventors: Michael R. Hsing, Anthonius Bakker
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Patent number: 8169801Abstract: Voltage converters with integrated low power leaker device and associated methods are disclosed herein. In one embodiment, a voltage converter includes a switch configured to convert a first electrical signal into a second electrical signal different than the first electrical signal. The voltage converter also includes a controller operatively coupled to the switch and a leaker device electrically coupled to the controller. The controller is configured to control the on and off gates of the switch, and the leaker device is configured to deliver power to the controller. The leaker device and the switch are formed on a first semiconductor substrate, and the controller is formed on second semiconductor substrate separate from the first semiconductor substrate.Type: GrantFiled: May 28, 2009Date of Patent: May 1, 2012Assignee: Monolithic Power Systems, Inc.Inventors: Michael R. Hsing, Ognjen Milic, Tiesheng Li
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Patent number: 8084811Abstract: Power devices with super junctions and associated methods of manufacturing are disclosed herein. In one embodiment, a method for forming a power device includes forming an epitaxial layer on a substrate material and forming a trench in the epitaxial layer. The trench has a first sidewall, a second sidewall, and a bottom between the first and second sidewalls. The method also includes forming an insulation material on at least one of the first and second sidewalls of the trench and diffusing a dopant into the epitaxial layer via at least one of the first and second sidewalls of the trench via the insulation material.Type: GrantFiled: October 8, 2009Date of Patent: December 27, 2011Assignee: Monolithic Power Systems, Inc.Inventors: Donald R. Disney, Michael R. Hsing
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Publication number: 20110227147Abstract: RESURF effect devices with both relatively deep trenches and relatively deep implants are described herein. Also, methods of fabricating such devices are described herein. A RESURF effect device may include alternating regions of first and second conductivity types where each of the second regions includes an implant region formed into a trench region of the second region.Type: ApplicationFiled: March 19, 2010Publication date: September 22, 2011Inventors: Tiesheng Li, Michael R. Hsing, Deming Xiao
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Publication number: 20110188218Abstract: A multi-phase voltage regulator is disclosed where each phase is comprised of an array of high and low side transistors that are integrated onto a single substrate. Further, a system of mounting the voltage regulator onto a flip chip and lead frame is disclosed wherein the source and drain lines form an interdigital pattern.Type: ApplicationFiled: February 2, 2010Publication date: August 4, 2011Inventors: Michael R. Hsing, Anthonius Bakken
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Publication number: 20110084333Abstract: Power devices with super junctions and associated methods of manufacturing are disclosed herein. In one embodiment, a method for forming a power device includes forming an epitaxial layer on a substrate material and forming a trench in the epitaxial layer. The trench has a first sidewall, a second sidewall, and a bottom between the first and second sidewalls. The method also includes forming an insulation material on at least one of the first and second sidewalls of the trench and diffusing a dopant into the epitaxial layer via at least one of the first and second sidewalls of the trench via the insulation material.Type: ApplicationFiled: October 8, 2009Publication date: April 14, 2011Inventors: Donald R. Disney, Michael R. Hsing
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Publication number: 20110068410Abstract: A floorplan for a die having three high-voltage transistors for power applications is described. The three high-voltage transistors are specifically placed in relation to each other to optimize operation.Type: ApplicationFiled: March 30, 2010Publication date: March 24, 2011Inventors: Martin E. Garnett, Michael R. Hsing
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Publication number: 20110068377Abstract: In one embodiment, a junction field effect transistor having a substrate, wherein formed on the substrate is a graded n-doped region having a high doping concentration in an inner region and a low doping concentration in an outer region, with a p-doped buried region adjacent to the graded n-doped region near the outer region, and a spiral resistor connected to the graded n-doped region at its inner region and at its outer region. An ohmic contact at the inner region provides the drain, an ohmic contact at the outer region provides the source, and an ohmic contact at the substrate provides the gate.Type: ApplicationFiled: September 18, 2009Publication date: March 24, 2011Inventors: Michael R. Hsing, Martin E. Garnett, Ognjen Milic
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Publication number: 20110062554Abstract: In one embodiment, a graded n-doped region surrounding a well, and a spiral resistor connected to the well and to a p-doped region surrounding the graded n-doped region.Type: ApplicationFiled: September 17, 2009Publication date: March 17, 2011Inventors: Michael R. Hsing, James C. Moyer
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Publication number: 20100302810Abstract: Voltage converters with integrated low power leaker device and associated methods are disclosed herein. In one embodiment, a voltage converter includes a switch configured to convert a first electrical signal into a second electrical signal different than the first electrical signal. The voltage converter also includes a controller operatively coupled to the switch and a leaker device electrically coupled to the controller. The controller is configured to control the on and off gates of the switch, and the leaker device is configured to deliver power to the controller. The leaker device and the switch are formed on a first semiconductor substrate, and the controller is formed on second semiconductor substrate separate from the first semiconductor substrate.Type: ApplicationFiled: May 28, 2009Publication date: December 2, 2010Inventors: Michael R. Hsing, Ognjen Milic, Tiesheng Li
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Publication number: 20100252918Abstract: The present invention discloses a multi-die package which facilitates heat dissipation for a high power consumption die. In the package, part of the lead frame is bent so as to be exposed at the surface of the package. On the opposite side of the exposed surface, a high power consumption die is attached. The other die with lower power consumption is not at the surface of the multi-die package.Type: ApplicationFiled: April 6, 2009Publication date: October 7, 2010Inventors: Hunt H. Jiang, Eric Yang, Michael R. Hsing, Frank Ren
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Patent number: 6518138Abstract: An LDMOS transistor formed in an N-type substrate. A polysilicon gate is formed atop the N-type substrate. A P-type well is formed in the N-type substrate extending from the source side to under the polysilicon gate. A N+ source region is formed in the P-type well and adjacent to the polysilicon gate. A N+ drain region is formed in the N-type substrate and in the drain side of the polysilicon gate. Finally, an N-type drift region is formed between the N+ drain region and the polysilicon gate, wherein the N-type drift region does not extend to said polysilicon gate.Type: GrantFiled: February 28, 2001Date of Patent: February 11, 2003Assignee: Monolithic Power Systems, Inc.Inventor: Michael R. Hsing
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Publication number: 20010009790Abstract: An LDMOS transistor formed in an N-type substrate. A polysilicon gate is formed atop the N-type substrate. A P-type well is formed in the N-type substrate extending from the source side to under the polysilicon gate. A N+source region is formed in the P-type well and adjacent to the polysilicon gate. A N+drain region is formed in the N-type substrate and in the drain side of the polysilicon gate. Finally, an N-type drift region is formed between the N+drain region and the polysilicon gate, wherein the N-type drift region does not extend to said polysilicon gate.Type: ApplicationFiled: February 28, 2001Publication date: July 26, 2001Inventor: Michael R. Hsing
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Patent number: 6252278Abstract: An LDMOS transistor formed in an N-type substrate. A polysilicon gate is formed atop the N-type substrate. A P-type well is formed in the N-type substrate extending from the source side to under the polysilicon gate. A N+ source region is formed in the P-type well and adjacent to the polysilicon gate. A N+ drain region is formed in the N-type substrate and in the drain side of the polysilicon gate. Finally, an N-type drift region is formed between the N+ drain region and the polysilicon gate, wherein the N-type drift region does not extend to said polysilicon gate.Type: GrantFiled: May 18, 1998Date of Patent: June 26, 2001Assignee: Monolithic Power Systems, Inc.Inventor: Michael R. Hsing
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Patent number: 5556796Abstract: A method in accordance with one embodiment of the present invention may be used to self-align isolation regions, sinkers, and wells. In this improved method, P+ isolation regions, N+ sinkers, and P-wells are defined using the same masking step used to define the N-wells. The use of a single masking step to initially define the P+ isolation regions, N+ sinkers, N-wells, and P-wells results in the self-alignment of these regions. Several critical mask alignments are thereby eliminated, thus avoiding/simplifying fabrication steps, conserving die area, and allowing increased component density.Type: GrantFiled: April 25, 1995Date of Patent: September 17, 1996Assignee: Micrel, Inc.Inventors: Martin E. Garnett, Michael R. Hsing
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Patent number: 5517046Abstract: A lateral DMOS transistor structure formed in N-type silicon is disclosed which incorporates a special N-type enhanced drift region. In one embodiment, a cellular transistor with a polysilicon gate mesh is formed over an N epitaxial layer with P body regions, P.sup.+ body contact regions, N.sup.+ source and drain regions, and N enhanced drift regions. The N enhanced drift regions are more highly doped than the epitaxial layer and extend between the drain regions and the gate. Metal strips are used to contact the rows of source and drain regions. The N enhanced drift regions serve to significantly reduce on-resistance without significantly reducing breakdown voltage.Type: GrantFiled: February 6, 1995Date of Patent: May 14, 1996Assignee: Micrel, IncorporatedInventors: Michael R. Hsing, Martin E. Garnett, James C. Moyer, Martin J. Alter, Helmuth R. Litfin