Abstract: Presented is a method of conformally coating a light emitting semiconductor structure with a phosphor layer to produce a substantially uniform white light. A light emitting semiconductor structure is coupled to a submount, a first bias voltage is applied to the submount, and a second bias voltage is applied to a solution of charged phosphor particles. The charged phosphor particles deposit on the conductive surfaces of the light emitting semiconductor structure. If the light emitting semiconductor structure includes a nonconductive substrate, the light emitting semiconductor structure is coated with an electroconductive material to induce phosphor deposition. The electrophoretic deposition of the phosphor particles creates a phosphor layer of uniform thickness that produces uniform white light without colored rings.

Abstract: The present invention is an inverted III-nitride light-emitting device (LED) with enhanced total light generating capability. A large area device has an n-electrode that interposes the p-electrode metallization to provide low series resistance. The p-electrode metallization is opaque, highly reflective, and provides excellent current spreading. The p-electrode at the peak emission wavelength of the LED active region absorbs less than 25% of incident light per pass. A submount may be used to provide electrical and thermal connection between the LED die and the package. The submount material may be Si to provide electronic functionality such as voltage-compliance limiting operation. The entire device, including the LED-submount interface, is designed for low thermal resistance to allow for high current density operation. Finally, the device may include a high-refractive-index (n>1.8) superstrate.

Abstract: The present invention is an inverted III-nitride light-emitting device (LED)) with enhanced total light generating capability. A large area device has an n-electrode that interposes the p-electrode metallization to provide low series resistance. The p-electrode metallization is opaque, highly reflective, and provides excellent current spreading. The p-electrode at the peak emission wavelength of the LED active region absorbs less than 25% of incident light per pass. A submount may be used to provide electrical and thermal connection between the LED die and the package. The submount material may be Si to provide electronic functionality such as voltage-compliance limiting operation. The entire device, including the LED-submount interface, is designed for low thermal resistance to allow for high current density operation. Finally, the device may include a high-refractive-index (n>1.8) superstrate.

Abstract: A light-emitting device includes: a semiconductor structure formed on one side of a substrate, the semiconductor structure having a plurality of semiconductor layers and an active region within the layers; and first and second conductive electrodes contacting respectively different semiconductor layers of the structure; the substrate comprising a material having a refractive index n>2.0 and light absorption coefficient &agr;, at the emission wavelength of the active region, of &agr;>3 cm−1. In a preferred embodiment, the substrate material has a refractive index n>2.3, and the light absorption coefficient, &agr;, of the substrate material is &agr;<1 cm−1.

Abstract: The extraction efficiency of a light emitting device can be improved by making the absorbing device layers as thin as possible. The internal quantum efficiency decreases as the device layers become thinner. An optimal active layer thickness balances both effects. An AlGaInP LED includes a substrate and device layers including an AlGaInP lower confining layer of a first conductivity type, an AlGaInP active region of a second conductivity type, and an AlGaInP upper confining layer of a second conductivity type. The absorbance of the active region is at least one fifth of the total absorbance in the light-emitting device. The device optionally includes at least one set-back layers of AlGaInP interposing one of confining layer and active region. The p-type upper confining layer may be doped with oxygen improve the reliability.

Abstract: A light-emitting semiconductor device includes a stack of layers including an active region. The active region includes a semiconductor selected from the group consisting of III-Phosphides, III-Arsenides, and alloys thereof. A superstrate substantially transparent to light emitted by the active region is disposed on a first side of the stack. First and second electrical contacts electrically coupled to apply a voltage across the active region are disposed on a second side of the stack opposite to the first side. In some embodiments, a larger fraction of light emitted by the active region exits the stack through the first side than through the second side. Consequently, the light-emitting semiconductor device may be advantageously mounted as a flip chip to a submount, for example.

Abstract: Light emitting devices having a vertical optical path, e.g. a vertical cavity surface emitting laser or a resonant cavity light emitting or detecting device, having high quality mirrors may be achieved using wafer bonding or metallic soldering techniques. The light emitting region interposes one or two reflector stacks containing dielectric distributed Bragg reflectors (DBRs). The dielectric DBRs may be deposited or attached to the light emitting device. A host substrate of GaP, GaAs, InP, or Si is attached to one of the dielectric DBRs. Electrical contacts are added to the light emitting device.

Abstract: A method for fabricating a light-emitting semiconductor device including a III-Nitride quantum well layer includes selecting a facet orientation of the quantum well layer to control a field strength of a piezoelectric field and/or a field strength of a spontaneous electric field in the quantum well layer, and growing the quantum well layer with the selected facet orientation. The facet orientation may be selected to reduce the magnitude of a piezoelectric field and/or the magnitude of a spontaneous electric field, for example. The facet orientation may also be selected to control or reduce the magnitude of the combined piezoelectric and spontaneous electric field strength. As a result of the reduced magnitude of piezoelectric, spontaneous, or combined piezoelectric and spontaneous electric field strengths in their quantum well layers, light-emitting devices in accordance with the present invention may generate light with increased efficiency compared to prior art devices.

Abstract: The present invention is an inverted III-nitride light-emitting device (LED) with enhanced total light generating capability. A large area device has an n-electrode that interposes the p-electrode metallization to provide low series resistance. The p-electrode metallization is opaque, highly reflective, and provides excellent current spreading. The p-electrode at the peak emission wavelength of the LED active region absorbs less than 25% of incident light per pass. A submount may be used to provide electrical and thermal connection between the LED die and the package. The submount material may be Si to provide electronic functionality such as voltage-compliance limiting operation. The entire device, including the LED-submount interface, is designed for low thermal resistance to allow for high current density operation. Finally, the device may include a high-refractive-index (n>1.8) superstrate.

Abstract: The present invention enhances the light extraction from the topside of the LED by an appropriate choice of the spacing from the active region to the reflective ohmic contact. Proper selection of the spacing from the active region to the reflective contact causes the interference pattern of upwardly-directed light to concentrate light within the escape cone for emission. Appropriate spacings are shown to be approximately &lgr;n/4, and to lie in the ranges 2.3 &lgr;n/4≦d≦3.1 &lgr;n/4 (favorably ≈2.6 &lgr;n/4), and 4.0 &lgr;n/4≦d≦4.9 &lgr;n/4 (favorably ≈4.5 &lgr;n/4). Extraction of light is thereby enhanced.

Abstract: Light emitting devices with improved light extraction efficiency are provided. The light emitting devices have a stack of layers including semiconductor layers comprising an active region. The stack is bonded to a transparent optical element having a refractive index for light emitted by the active region preferably greater than about 1.5, more preferably greater than about 1.8. A method of bonding a transparent optical element (e.g., a lens or an optical concentrator) to a light emitting device comprising an active region includes elevating a temperature of the optical element and the stack and applying a pressure to press the optical element and the light emitting device together. A block of optical element material may be bonded to the light emitting device and then shaped into an optical element. Bonding a high refractive index optical element to a light emitting device improves the light extraction efficiency of the light emitting device by reducing loss due to total internal reflection.

Abstract: Light emitting devices having a vertical optical path, e.g. a vertical cavity surface emitting laser or a resonant cavity light emitting or detecting device, having high quality mirrors may be achieved using wafer bonding or metallic soldering techniques. The light emitting region interposes one or two reflector stacks containing dielectric distributed Bragg reflectors (DBRs). The dielectric DBRs may be deposited or attached to the light emitting device. A host substrate of GaP, GaAs, InP, or Si is attached to one of the dielectric DBRs. Electrical contacts are added to the light emitting device.

Abstract: The invention is a method for designing semiconductor light emitting devices such that the side surfaces (surfaces not parallel to the epitaxial layers) are formed at preferred angles relative to vertical (normal to the plane of the light-emitting active layer) to improve light extraction efficiency and increase total light output efficiency. Device designs are chosen to improve efficiency without resorting to excessive active area-yield loss due to shaping. As such, these designs are suitable for low-cost, high-volume manufacturing of semiconductor light-emitting devices with improved characteristics.

Abstract: Devices and techniques for fabricating InAlGaN light-emitting devices are described that result from the removal of light-emitting layers from the sapphire growth substrate. In several embodiments, techniques for fabricating a vertical InAlGaN light-emitting diode structure that result in improved performance and or cost-effectiveness are described. Furthermore, metal bonding, substrate liftoff, and a novel RIE device separation technique are employed to efficiently produce vertical GaN LEDs on a substrate chosen for its thermal conductivity and ease of fabrication.

Abstract: Light emitting devices having a vertical optical path, e.g. a vertical cavity surface emitting laser or a resonant cavity light emitting or detecting device, having high quality mirrors may be achieved using wafer bonding or metallic soldering techniques. The light emitting region interposes one or two reflector stacks containing dielectric distributed Bragg reflectors (DBRs). The dielectric DBRs may be deposited or attached to the light emitting device. A host substrate of GaP, GaAs, InP, or Si is attached to one of the dielectric DBRs. Electrical contacts are added to the light emitting device.

Abstract: The extraction efficiency of a light emitting device can be improved by making the absorbing device layers as thin as possible. The internal quantum efficiency decreases as the device layers become thinner. An optimal active layer thickness balances both effects. An AlGaInP LED includes a substrate and device layers including an AlGaInP lower confining layer of a first conductivity type, an AlGaInP active region of a second conductivity type, and an AlGaInP upper confining layer of a second conductivity type. The absorbance of the active region is at least one fifth of the total absorbance in the light-emitting device. The device optionally includes at least one set-back layers of AlGaInP interposing one of confining layer and active region. The p-type upper confining layer may be doped with oxygen improve the reliability.

Abstract: Light emitting devices having a vertical optical path, e.g. a vertical cavity surface emitting laser or a resonant cavity light emitting or detecting device, having high quality mirrors may be achieved using wafer bonding or metallic soldering techniques. The light emitting region interposes one or two reflector stacks containing dielectric distributed Bragg reflectors (DBRs). The dielectric DBRs may be deposited or attached to the light emitting device. A host substrate of GaP, GaAs, InP, or Si is attached to one of the dielectric DBRs. Electrical contacts are added to the light emitting device.

Abstract: The invention is a method for designing semiconductor light emitting devices such that the side surfaces (surfaces not parallel to the epitaxial layers) are formed at preferred angles relative to vertical (normal to the plane of the light-emitting active layer) to improve light extraction efficiency and increase total light output efficiency. Device designs are chosen to improve efficiency without resorting to excessive active area-yield loss due to shaping. As such, these designs are suitable for low-cost, high-volume manufacturing of semiconductor light-emitting devices with improved characteristics.

Abstract: The invention is a method for designing semiconductor light emitting devices such that the side surfaces (surfaces not parallel to the epitaxial layers) are formed at preferred angles relative to vertical (normal to the plane of the light-emitting active layer) to improve light extraction efficiency and increase total light output efficiency. Device designs are chosen to improve efficiency without resorting to excessive active area-yield loss due to shaping. As such, these designs are suitable for low-cost, high-volume manufacturing of semiconductor light-emitting devices with improved characteristics.

Abstract: The invention is a method for designing semiconductor light emitting devices such that the side surfaces (surfaces not parallel to the epitaxial layers) are formed at preferred angles relative to vertical (normal to the plane of the light-emitting active layer) to improve light extraction efficiency and increase total light output efficiency. Device designs are chosen to improve efficiency without resorting to excessive active area-yield loss due to shaping. As such, these designs are suitable for low-cost, high-volume manufacturing of semiconductor light-emitting devices with improved characteristics.