Abstract: A single board computer system radiation hardened for space flight includes a printed circuit board having a top side and bottom side; a reconfigurable field programmable gate array (FPGA) processor device disposed on the top side; a connector disposed on the top side; a plurality of peripheral components mounted on the bottom side; and wherein a size of the single board computer system is not greater than approximately 7 cm×7 cm.

Abstract: A stacking pin alignment fixture for a stacking connector includes a substrate and a plurality of openings defined in the substrate, the plurality of openings being arranged in a predefined pattern. The predefined pattern corresponds to a pattern of a field of straight pins arranged on the stacking connector.

Abstract: Embodiments may provide a radiation hardened 10BASE-T Ethernet interface circuit suitable for space flight and in compliance with the IEEE 802.3 standard for Ethernet. The various embodiments may provide a 10BASE-T Ethernet interface circuit, comprising a field programmable gate array (FPGA), a transmitter circuit connected to the FPGA, a receiver circuit connected to the FPGA, and a transformer connected to the transmitter circuit and the receiver circuit. In the various embodiments, the FPGA, transmitter circuit, receiver circuit, and transformer may be radiation hardened.

Abstract: A method of safe to mate testing includes providing a file of netlist signals where each signal defines a first connection to one or more components of a unit under test, connecting a first terminal of a measuring device to a first netlist signal and connecting a second terminal of the measuring device to a second netlist signal, performing a plurality of first resistive measurements by applying power having a first polarity between the first and second netlist signals, performing at least one second resistive measurement by applying power having a second polarity to the first and second netlist signals, and recording an average of the first resistive measurements and, if the second polarity measurement yields a negative result, an indication that a reactive load is connected between the first and second netlist signals.

Abstract: Embodiments may provide a radiation hardened 10BASE-T Ethernet interface circuit suitable for space flight and in compliance with the IEEE 802.3 standard for Ethernet. The various embodiments may provide a 10BASE-T Ethernet interface circuit, comprising a field programmable gate array (FPGA), a transmitter circuit connected to the FPGA, a receiver circuit connected to the FPGA, and a transformer connected to the transmitter circuit and the receiver circuit. In the various embodiments, the FPGA, transmitter circuit, receiver circuit, and transformer may be radiation hardened.

Abstract: An on-board space processing system capable of processing data at more than 2500 Million Instructions Per Second on board a spacecraft is disclosed. The system may be a cube, and may include processor card and a hybrid card. The processor card may include a processor that may be programmable and reprogrammable prior to, and during, spaceflight. The hybrid card may include a field programmable gate array module that may program and reprogram the processor prior to, and during, the spaceflight.

Abstract: A processing system having a small form factor and configured to connect to an external platform. The processing system includes input interfaces configured to receive an input signal to be processed; a radiation tolerant field programmable gate array including processors configured to process the input signal; memory containing reconfigurable instructions for the processors that, when the reconfigurable instructions are executed, process the input signal and obtain the output signal; output interfaces configured to send the output signal to the external platform; and a reset logic element configured to selectively reset the field programmable gate array and at least one of the processors in response to a reset command. The input interfaces include at least one gigabit Ethernet interface and at least one space-rated balanced voltage digital interface circuit.

Abstract: A space qualified local area network includes a plurality of stations, a switch in communication with the plurality of stations, and a network interface controller associated with each station. The network interface controller includes a media access controller having a medium-independent interface and a physical layer. The physical layer includes a data-strobe encoder for combining a first data signal and a strobe signal to produce an output signal, a low voltage differential signaling driver for transmitting the output signal, a low voltage differential signaling receiver for receiving an input signal, and a clock recovery decoder for extracting a second data signal and a clock signal from the input signal.