Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

Abstract: A communication system (100) for alerting a user based upon content of messages transmitted to the user includes a terminal (105) for generating and transmitting a message having first and second recipient identifications (IDs) and first and second alert codes. A radio receiver (110) receives the message and determines whether the first recipient ID is equivalent to an ID associated with the radio receiver (110). When the first recipient ID is equivalent to an ID associated with the radio receiver (110), the radio receiver (110) selects one of the at least first and second alert codes based upon a location of the first recipient ID within the message and generates an alert associated with the one of the at least first and second alert codes.

Abstract: A radio receiver (50) for establishing a message debiting system has a receiver (54) for receiving message information and a memory (104) for storing the received message information to be presented to a user of the radio receiver (50). The radio receiver (50) includes a debit meter (72) which indicates a number of available credit units for enabling the presentation of the stored message information. The stored message information is processed a decoder/controller (56) and a number of debit units is calculated from a parameter of the stored message information. The number of debit units of the stored message is debited from the indicated number of credit units of the debit meter to enable the presentation of the stored message information. The stored message is disabled from being presented to the user when the number of available credit units of the debit meter (72) is depleted.

Abstract: Method and apparatus for detecting and sectionalizing troubles on telephone lines automatically. Specifically, an embodiment for detecting and sectionalizing troubles on a telephone line connecting a switching machine and a subscriber telephone set connected thereto over the telephone line, includes apparatus which: (a) emits a pulse over the telephone line; (b) detects reflections of the pulse; and (c) and determines whether a reflection was received prior to the expiration of a predetermined time period. The predetermined period relates to a distance which is less than the length of the telephone line between the switching machine and the subscriber telephone set.

Abstract: Bus interconnection between the system busses of a multi-port communications controller and the busses of one or more multi-port adapters is facilitated with a new architecture for providing an interconnection controller. A programmably adjustable adapter and port interface controller is combined via a scannerless communications controller with a bus interconnection control logic that handles both DMA and interrupt mode data transfers for a large number of channels. The invention provides an improved apparatus and method for transferring data to or from numerous communication channel devices within a processor based communications system in such a manner that the optimum mode of data transfer may be individually programmed for each channel as system environment conditions demand.

Abstract: A multi-port communications controller and variable protocol adapter is described. The adapter utilizes a user programmable pluggable programming cartridge for defining individual communications port data service characteristics. The port data service characteristics are interpreted by a microprocessor which manages the interchange from port to port and to or from memory or a host system. Direct memory access or interrupt driven memory access modes of operation are individually selectable for each individual in bound and out bound communications channel. The communications protocols employed at each port may be of any standard type with the microprocessor in the adapter making the appropriate conversion. Communication speeds can be automatically recognized and matched for each port also.

Abstract: Both DMA access and character interrupt driven access modes of service are provided to multiple communication ports by an integrated arbitration DMA/interrupt controller utilizing its own resident randomly accessible memory. Pipelined logic control architecture for handling service mode adaptations for each individual port and for managing memory accesses to main system memory enables the use of the random access memory with its inherent time delays in a manner that virtually eliminates the effect of any time delay in overall memory access throughput.