Abstract: Port occupancy detection for connector panels is provided. In one embodiment, a connector panel comprises: a communications unit communicatively coupled to a network; and at least one modular port adapter assembly comprising: a plurality of communications couplers; and a plurality of port occupancy sensors each coupled to a sensor circuit. Each of the port occupancy sensors are configured to sense when the couplers are occupied. The panel communications unit obtains from the sensor circuit which of the couplers are occupied. The panel communications unit communicates port occupancy information to a gateway indicating circuit which of the couplers are occupied. A chassis including sidewalls extends between a front and a rear to define an interior, and including guides on the sidewalls. A plurality of blades mounted to the guides of the chassis, each blade including a midplane bus assembly configured to communicatively couple the sensor circuit to the panel communication unit.

Abstract: Extracting gallium and/or arsenic from materials comprising gallium arsenide is generally disclosed. In some example embodiments, a material comprising gallium arsenide may be exposed to a first heating condition to form a first exhaust. The first exhaust may be directed to an arsenic collection bed including aluminum, which may form aluminum arsenide. The material including gallium arsenide may be exposed to a second heating condition and/or a vacuum may be applied, which may form a second exhaust. The second exhaust may be directed to a gallium collection bed including aluminum, which may form gallium alloys of aluminum.

Abstract: Extracting gallium and/or arsenic from materials comprising gallium arsenide is generally disclosed. In some example embodiments, a material comprising gallium arsenide may be exposed to a first heating condition to form a first exhaust. The first exhaust may be directed to an arsenic collection bed including aluminum, which may form aluminum arsenide. The material including gallium arsenide may be exposed to a second heating condition and/or a vacuum may be applied, which may form a second exhaust. The second exhaust may be directed to a gallium collection bed including aluminum, which may form gallium alloys of aluminum.

Abstract: Extracting gallium and/or arsenic from materials comprising gallium arsenide is generally disclosed. In some example embodiments, a material comprising gallium arsenide may be exposed to a first heating condition to form a first exhaust. The first exhaust may be directed to an arsenic collection bed including aluminum, which may form aluminum arsenide. The material including gallium arsenide may be exposed to a second heating condition and/or a vacuum may be applied, which may form a second exhaust. The second exhaust may be directed to a gallium collection bed including aluminum, which may form gallium alloys of aluminum.

Abstract: Extracting gallium and/or arsenic from materials comprising gallium arsenide is generally disclosed. In some example embodiments, a material comprising gallium arsenide may be exposed to a first heating condition to form a first exhaust. The first exhaust may be directed to an arsenic collection bed including aluminum, which may form aluminum arsenide. The material including gallium arsenide may be exposed to a second heating condition and/or a vacuum may be applied, which may form a second exhaust. The second exhaust may be directed to a gallium collection bed including aluminum, which may form gallium alloys of aluminum.

Abstract: A technique is described whereby temperature gradients are created within a semiconductor wafer. Temperature sensitive etching and/or deposition processes are then employed. These temperature sensitive processes proceed at different rates in regions with different temperatures. To reduce pinch off in etching processes, a temperature sensitive etch process is selected and a temperature gradient is created between the surface and subsurface of a wafer such that the etching process proceeds more slowly at the surface than deeper in the wafer. This reduces “crusting” of solid reaction products at trench openings, thereby eliminating pinch off in many cases. Similar temperature-sensitive deposition processes can be employed to produce void-free high aspect ratio conductors and trench fills.

Abstract: Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. Then, a COR pre-clean is performed and the recesses are filled by epitaxial deposition. The epi can be in-situ doped or subsequently implanted to form source/drain extensions. Alternatively, the etch is immediately followed by the COR pre-clean, which is followed by epitaxial deposition to fill the recesses. During the epitaxial deposition process, the deposited material is doped to form in-situ doped halos and, then, the dopant is switched to form in-situ doped source/drain extensions adjacent to the halos. Alternatively, after the in-situ doped halos are formed the deposition process is performed without dopants and an implant is used to form source/drain extensions.

Abstract: A technique is described whereby temperature gradients are created within a semiconductor wafer. Temperature sensitive etching and/or deposition processes are then employed. These temperature sensitive processes proceed at different rates in regions with different temperatures. To reduce pinch off in etching processes, a temperature sensitive etch process is selected and a temperature gradient is created between the surface and subsurface of a wafer such that the etching process proceeds more slowly at the surface than deeper in the wafer. This reduces “crusting” of solid reaction products at trench openings, thereby eliminating pinch off in many cases. Similar temperature-sensitive deposition processes can be employed to produce void-free high aspect ratio conductors and trench fills.

Abstract: A method for removing a material from a trench in a semiconductor. The method includes placing the semiconductor in a vacuum chamber, admitting a reactant into the chamber at a pressure to form a film of the reactant on a surface of the material, controlling the composition and residence time of the film on the surface of the material to etch at least a portion of the material, and removing any unwanted reactant and reaction product from the chamber or the surface of the material.

Abstract: Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. Then, a COR pre-clean is performed and the recesses are filled by epitaxial deposition. The epi can be in-situ doped or subsequently implanted to form source/drain extensions. Alternatively, the etch is immediately followed by the COR pre-clean, which is followed by epitaxial deposition to fill the recesses. During the epitaxial deposition process, the deposited material is doped to form in-situ doped halos and, then, the dopant is switched to form in-situ doped source/drain extensions adjacent to the halos. Alternatively, after the in-situ doped halos are formed the deposition process is performed without dopants and an implant is used to form source/drain extensions.

Abstract: A temperature-controlled substrate holder having a high temperature substrate chuck is mounted within a chemical treatment chamber. The temperature-controlled substrate holder secures a substrate and maintains the substrate at a temperature that ranges from about 10° C. up to about 150° C. during execution of a chemical oxide removal process.

Abstract: Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. Then, a COR pre-clean is performed and the recesses are filled by epitaxial deposition. The epi can be in-situ doped or subsequently implanted to form source/drain extensions. Alternatively, the etch is immediately followed by the COR pre-clean, which is followed by epitaxial deposition to fill the recesses. During the epitaxial deposition process, the deposited material is doped to form in-situ doped halos and, then, the dopant is switched to form in-situ doped source/drain extensions adjacent to the halos. Alternatively, after the in-situ doped halos are formed the deposition process is performed without dopants and an implant is used to form source/drain extensions.

Abstract: Photoelectron emissions are used to detect an endpoint of a thickness alteration of a topmost layer in a set of layers undergoing patterning. The set of layers are irradiated, which causes an emission of photoelectrons. Upon receipt of or absence of a photoelectron emission, patterning endpoint is detected.

Abstract: An atomic force microscope (AFM) having a hollowed cantilever ending in a hollowed tip is described, wherein the end of the tip is immersed in a liquid. The AFM includes a gas source that provides and controls the flow of gas into the hollowed tip. The flow rate of the gas is regulated to form and sustain a static bubble at the end of the hollowed tip. The formation of the static bubble is verified optically. A gas control manifold allows an easy switch of gasses that are fed into the probe tip. The gas that is introduced acts like a chemically modified tip, and is selected to increase the deflection signal for the material of interest. The tip of the present invention is a highly versatile AFM tool that is easily adjusted to provide optimized imaging for a wide variety of materials, in contrast with standard AFMs that require a plethora of chemically modified tips to obtain equivalent results.

Abstract: A non-destructive in-situ elemental profiling of a layer in a set of layers method and system are disclosed. In one embodiment, a first emission of a plurality of photoelectrons is caused from the layer to be elementally profiled. An elemental profile of the layer is determined based on the emission. In another embodiment, a second emission of a plurality of photoelectrons is also received from the layer, and an elemental profile is determined by comparison of the resulting signals. A process that is altering the layer can then be controlled “on-the-fly” to obtain a desired material composition. Since the method can be employed in-situ and is non-destructive, it reduces turn around time and lowers wafer consumption. The invention also records the composition of all processed wafers, hence, removing the conventional statistical sampling problem.

Abstract: Detection of weak ion currents scattered from a sample by an ion beam is improved by the use of a multiplier system in which a conversion electrode converts incident ions to a number of secondary electrons multiplied by a multiplication factor, the secondary electrons being attracted to an electron detector by an appropriate bias. In one version, the detector is a two stage system, in which the secondary electrons strike a scintillator that emits photons that are detected in a photon detector such as a photomultiplier or a CCD.

Abstract: The present invention is directed to methods for editing copper features embedded within an organic body by exposing at least a portion of a top surface of the copper feature, forming a mill box there-over and then simultaneously milling both the copper feature and any organic material exposed through the mill box in a single step using an ion beam in combination with a XeF2 gas for a dwell time of at least 10 milliseconds. The invention dramatically increases the efficiency of Focused Ion Beam milling of copper features embedded in organic layers by milling these features in a gas-depleted environment at significantly increased dwell time while avoiding the problems of graphitization, destruction of the organic layer and metal redeposition.

Abstract: A method and structure for an apparatus for removing metal from an integrated circuit structure is disclosed. A container holds an integrated circuit structure that has a metal portion. An electronic device connected to the container produces an electronic field proximate to a limited region of the metal portion. A first supply connected to the container supplies an oxidizing agent within the container. A solvent supply connected to the container supplies solvent to the limited region of the metal portion.

Abstract: The present invention is directed to methods for editing copper features embedded within an organic body by exposing at least a portion of a top surface of the copper feature, forming a mill box there-over and then simultaneously milling both the copper feature and any organic material exposed through the mill box in a single step using an ion beam in combination with a XeF2 gas for a dwell time of at least 10 milliseconds. The invention dramatically increases the efficiency of Focused Ion Beam milling of copper features embedded in organic layers by milling these features in a gas-depleted environment at significantly increased dwell time while avoiding the problems of graphitization, destruction of the organic layer and metal redeposition.

Abstract: A method and structure for an apparatus for removing metal from an integrated circuit structure is disclosed. A container holds an integrated circuit structure that has a metal portion. An electronic device connected to the container produces an electronic field proximate to a limited region of the metal portion. A first supply connected to the container supplies an oxidizing agent within the container. A solvent supply connected to the container supplies solvent to the limited region of the metal portion.