Abstract: In one embodiment, a clock divider circuit preserves characteristics of both a rising edge and a falling edge of a source clock. The clock divider circuit may include a counter, a flip-flop, and an output. The counter is configured to divide a source clock signal into a divided clock signal. The flip-flop is configured to receive the divided clock signal and an inverse of the source clock signal to trigger the flip-flop. The output includes a logic gate configured to output a final clock signal based on a logical union of an output of the flip-flop and the divided clock signal. The final clock signal includes the jitter from the falling edge of the source clock and the jitter from the rising edge of the source clock.

Abstract: A power-on reset circuit for providing a reset signal to an active device on an integrated circuit (IC). The circuit includes a RC circuit for producing a reset signal until its capacitor fully charges. The circuit also includes a voltage detector for preventing the charge from collecting on the capacitor of the RC circuit until the voltage is at a functional level.