Abstract: A servo controller includes a first device that determines an adjusted servo-to-servo skew value. A servo field timer increments a timer value between consecutive servo fields, receives the adjusted servo-to-servo skew value, and adjusts an incremented timer value between the consecutive servo fields based on the adjusted servo-to-servo skew value.

Abstract: A track follow controller includes a burst selector selecting at least one burst pair based on burst pair selection data. A linear position calculator calculates a primary head position and a secondary head position based on the at least one burst pair, and calculates a head linear position based on the primary head position and the secondary head position.

Abstract: A system-on-chip including a processor, a control module, a first plurality of data registers, a second plurality of data registers, a plurality of address registers, and a first control module. The first plurality of data registers are configured to store data. The processor is configured to respectively write addresses corresponding to selected ones of the first plurality of data registers in the plurality of address registers. The second plurality of data registers are configured to receive data from the selected ones of the first plurality of data registers. In response to a request from the processor for a first address, the first control module is configured to provide data to the processor from the second plurality of data registers in response to the first address matching an address stored in the plurality of address registers, and otherwise provide data to the processor from the first plurality of data registers.

Abstract: A servo controller for a disk drive controller comprising a storage device that stores communication information for a plurality of devices and a serial port controller located on the servo controller that communicates with the storage device, that receives a request to communicate with one of the plurality of devices, and that allows communication between at least one processor and the one of the plurality of devices according to the stored communication information and the request, wherein each of the plurality of devices uses a different protocol.

Abstract: An embedded disk controller (“controller”) having a servo controller is provided. The controller also includes a servo controller interface with a speed matching module and a pipeline control module such that at least two processors share memory mapped registers without conflicts. The processors operate at different frequencies, while the servo-controller and the servo controller interface operate in same or different frequency domains. The pipeline control module resolves conflict between the first and second processor transaction. The speed matching module ensures communication without inserting wait states in a servo controller interface clock domain for write access to the servo controller and there is no read conflicts between the first and second processor. The controller also includes a hardware mechanism for indivisible register acess to the first or second processor. The hardware mechanisim includes a hard semaphore and/or soft semaphore.

Abstract: A system-on-chip (SOC) includes a processor, a controller module for a hard disk drive, and a communication bus that provides a communication link between the processor and the controller module. The communication bus includes a multiplexer that includes an output and an input that receives data from a selected one of N registers associated with the controller module and propagates the data to the output, M address registers that store addresses of up to M ones of the N registers, M data registers that receive pre-fetch data that corresponds to the data from the output from the M ones of the N registers, and a second multiplexer that includes a second output and that reads the pre-fetch data from the M data registers and propagates the pre-fetch data to the second output. M and N are positive integers greater than two and N is greater than M.

Abstract: A track follow controller includes a burst selector selecting at least one burst pair based on burst pair selection data. A linear position calculator calculates a primary head position and a secondary head position based on the at least one burst pair, and calculates a head linear position based on the primary head position and the secondary head position.

Abstract: A system and method for a servo controller (SC) used in an embedded disk controller for adjusting stored servo skew values based on measured skew values is provided. The system includes, a servo timing controller, wherein the servo timing controller includes a first register that stores measured servo skew values at a given time; a first set of registers that receive stored skew values and the measured skew values; and firmware that adjusts the skew values based on the measured skew values measured by a reference timer. The process includes, measuring actual skew values during a head change in a read operation; comparing the measured skew values with the stored skew values; adjusting the skew value based on the comparison; and adjusting a servo field timer based on the adjusted skew value.

Abstract: A position error calculator for an embedded disk controller including a burst selector that selects a burst pair based on a burst pair format. The burst pair format includes at least a first burst pair format that includes x bursts and a second burst pair format that includes y bursts and x is not equal to y. A linear position calculator calculates head linear position based on the burst pair format.

Abstract: A servo controller for an embedded disk controller comprises a read channel interface that includes a programmable control logic that receives a servo field detected signal from a module that detects a servo field start bit. A memory in the read channel interface is enabled by the programmable control logic for receiving servo field data from a read channel device, wherein the programmable control logic is configured to operate in a first mode and a second mode allowing the servo controller to process servo data from the read channel device. The servo controller processes the servo data using first and second data widths during the first and second modes, respectively.

Abstract: A track follow controller (“TFC”) in an embedded disk controller is provided. The TFC includes, a position error calculator that determines a linear position of a head based on burst format and determines a position error based on the linear position and a target position; and a position error output compensator that receives a position error signal from the position error calculator and filters the position error signal. The burst format includes at least a first burst pair format that includes x bursts and a second burst pair format that includes y bursts, where x is unequal to y. The position error calculator includes a burst selector that can select a burst pair; a linear position calculator that calculates head linear position based on burst pair format; and an error calculator that determines the position error based on the linear position and target position.

Abstract: A system for an embedded disk controller is provided. The system includes a first main processor operationally coupled to a high performance bus; a second processor operationally coupled to a peripheral bus; a bridge that interfaces between the high performance and peripheral bus; an external bus controller coupled to the high performance bus and operationally coupled to external devices via an external bus interface; an interrupt controller module that can generate a fast interrupt to the first main processor; a history module coupled to the high performance and peripheral bus for monitoring bus activity; and a servo controller that is coupled to the second processor through a servo controller interface and provides real time servo controller information to the second processor. The second processor may be a digital signal processor that is operationally coupled to the first main processor through an interface.

Abstract: A system for collecting servo field data from programmable devices in embedded disk controllers. The system includes a servo controller with a read channel interface. The read channel interface includes a programmable control logic that receives a servo field detected signal from a module that detects a servo field start bit; and a register in the read channel interface that is enabled by the programmable control logic for receiving servo field data from a read channel device. The programmable control logic is configured to operate both in a two wire mode and in a three wire mode allowing the servo controller to process servo data from the read channel device.

Abstract: A serial port controller in an embedded disk drive controller is provided. The serial port controller includes a state machine that can access protocol information regarding plural devices operationally coupled to the serial port controller; a first register that can hold address information of the plural devices; and logic for enabling the plural devices for either a write or read request. The serial port controller also includes a second register for holding write data information for the plural devices; and a third register for holding read data information for the plural devices. The serial port controller reads programmed information regarding the plural device upon a client request; transmits the address of a device with whom communication is requested by the client; and transmits data to the plural devices, if the request by the client is to write data or collects data for a read request.

Abstract: A system for an embedded disk controller is provided. The system includes a first main processor operationally coupled to a high performance bus; a second processor operationally coupled to a peripheral bus; a bridge that interfaces between the high performance and peripheral bus; an external bus controller coupled to the high performance bus and operationally coupled to external devices via an external bus interface; an interrupt controller module that can generate a fast interrupt to the first main processor; a history module coupled to the high performance and peripheral bus for monitoring bus activity; and a servo controller that is coupled to the second processor through a servo controller interface and provides real time servo controller information to the second processor. The second processor may be a digital signal processor that is operationally coupled to the first main processor through an interface.

Abstract: An embedded disk controller (“controller”) having a servo controller is provided. The controller also includes a servo controller interface with a speed matching module and a pipeline control module such that at least two processors share memory mapped registers without conflicts. The processors operate at different frequencies, while the servo-controller and the servo controller interface operate in same or different frequency domains. The pipeline control module resolves conflict between the first and second processor transaction. The speed matching module ensures communication without inserting wait states in a servo controller interface clock domain for write access to the servo controller and there is no read conflicts between the first and second processor. The controller also includes a hardware mechanism for indivisible register access to the first or second processor. The hardware mechanism includes a hard semaphore and/or soft semaphore.

Abstract: In a system having an input signal set with at least two signals having mutually exclusive frequencies f1 and f2 being part of the input signal set, whose amplitude is represented in an input digital representation, the amplitudes of each of the at least two signals are digitally represented. A digital representation of the frequency of each of the signals is derived. A digital representation of the sine function and of the cosine function of the frequency of each of the signals is derived based on the digital representation of the frequency. The digital representations of each of the sine and cosine functions is mixed with the input digital representation to derive digital representations of the sine and cosine functions of each of the signals. The digital representations of the sine and cosine functions of each of the signals are processed to derive a digital representation of the amplitude of each of the signals.

Abstract: The present invention provides a programmable generic read channel control device and circuitry for generating an output signal to control read/write operations. The programmable generic read channel control device includes a set of extension timer, a set of configuration registers, a set of AND gates, and an OR gate. The extension timers are programmed to generate a set of pulses of programmable width in response to a read gate and write gate signal. Each of the pulses is defined by a leading edge pulse and a trailing edge pulse. The set of extension timers includes a short write gate extension timer configured to generate a write gate short leading edge pulse and a write gate short trailing edge pulse defining a write gate short pulse width. The configuration registers store a set of configuration data for the pulses with each configuration register storing one configuration data for either a leading edge or a trailing edge pulse of one of the pulses.

Abstract: The present invention provides a programmable ADC with bit conversion optimization and method therefor. The programmable ADC includes an amplifier, a programmable clock generator, a comparator, a successive approximation logic, a digital-to-analog converter, and a voltage converter. The amplifier is arranged to sample and hold an input analog signal to be converted into N digital data bits. The programmable clock generator generates a clock signal for each of the N-bits to trigger setting of one of the N-bit digital data bits such that each of the N bits is set during a time optimized for each bit. The comparator is coupled to receive and compare the input analog signal with a successively approximated analog signal to generate a digital output signal. The successive approximation logic is configured to successively set each of the N-bits in response to the digital output signal and the clock signal to generate a successively approximated N-bit digital data.

Abstract: An integrated servo system for a disk drive employing sector servo positioning information on concentric tracks of a recording medium utilizes a servo burst pattern with three sequentially occurring servo bursts. One burst is positioned to have a maximum amplitude plateau on a track centerline of alternate tracks, and the other two bursts have maximum plateau values at locations between the centerlines of adjacent tracks. The amplitudes of the bursts are sequentially detected by a peak detector and supplied to sample and hold circuitry for measuring their relative amplitudes. Discriminator circuitry utilizes a window to provide two samples of each transition in the servo pattern and compares the samples to detect different fields and events in the pattern.