Patents by Inventor Michael R. Spica

Michael R. Spica has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250208963
    Abstract: In some implementations, a device may cause a single host device to load data to a first memory device of a plurality of memory devices configured in a fabric. The device may cause the first memory device to propagate the data to one or more second memory devices, of the plurality of memory devices, via one or more peer-to-peer transfer operations to replicate the data from the first memory device to the one or more second memory devices without involvement of the single host device.
    Type: Application
    Filed: November 20, 2024
    Publication date: June 26, 2025
    Inventors: Michael R. SPICA, Thomas T. TANGELDER
  • Publication number: 20250173302
    Abstract: In some implementations, a control unit component of a compute express link (CXL) compliant memory device may transmit, to a generator component of the CXL compliant memory device, an indication of a type of test being performed for the CXL compliant memory device. The generator component may generate a set of instructions based on the type of test being performed for the CXL compliant memory device. The generator component may inject the set of instructions into a data path of the CXL compliant memory device. The control unit component and/or a comparator component of the CXL compliant memory device may extract a set of data from the data path, wherein the set of data is generated by the data path based on the set of instructions. The control unit component may determine a test result based on the set of data.
    Type: Application
    Filed: November 22, 2024
    Publication date: May 29, 2025
    Inventor: Michael R. SPICA
  • Patent number: 12142336
    Abstract: A detection is made by a processing device allocated to a memory device test board of a distributed test platform that a memory sub-system has engaged with a memory device test resource of the memory device test board. A test is identified to be performed for a memory device of the memory sub-system. The test includes first instructions to be executed by a memory sub-system controller of the memory sub-system in performance of the test and second instructions to be executed by the processing device in performance of the test. The second instructions are to cause one or more test condition components of the memory device test resource to generate one or more test conditions to be applied to the memory device while the memory sub-system executes the first instructions. Responsive to a transmission of the first instructions to the memory sub-system controller, the second instructions are executed.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: November 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Gary D. Hamor, Michael R. Spica, Donald Shepard, Patrick Caraher, João Elmiro da Rocha Chaves
  • Patent number: 12013734
    Abstract: A system receives event information associated with an event that corresponds to a temperature of a memory sub-system including memory devices encased in respective packages. The system determines whether the event information associated with the event satisfies a threshold condition. Responsive to determining that the event information associated with the event satisfies the threshold condition, the system causes a thermoelectric component (TEC) that is coupled to an external surface of each of the respective packages of the memory devices of the memory sub-system to transfer thermal energy between the TEC and the memory devices via thermal conduction.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: June 18, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Michael R. Spica
  • Patent number: 11960349
    Abstract: A memory sub-system comprises a power management component comprising a plurality of regulators configured to supply respective operating voltages for components of the memory sub-system. The power management component is configured to adjust a regulator voltage level provided to a particular component until an operation state change of the particular component is detected. The power management voltage level is further configured to determine a value of the regulator voltage level at which the operation state change of the particular component is detected.
    Type: Grant
    Filed: October 7, 2022
    Date of Patent: April 16, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Michael R. Spica, Patrick T. Caraher
  • Patent number: 11854637
    Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device is configured to switch an operating mode of the memory device between a test mode and a non-test mode. The system further includes a test mode access component that is configured to access the memory device while the memory device is in the test mode to perform a test mode operation.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: December 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Michael R. Spica, David G. Springberg
  • Publication number: 20230178163
    Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device is configured to switch an operating mode of the memory device between a test mode and a non-test mode. The system further includes a test mode access component that is configured to access the memory device while the memory device is in the test mode to perform a test mode operation.
    Type: Application
    Filed: January 31, 2023
    Publication date: June 8, 2023
    Inventors: Michael R. Spica, David G. Springberg
  • Patent number: 11581053
    Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device is configured to switch an operating mode of the memory device between a test mode and a non-test mode. The system further includes a test mode access component that is configured to access the memory device while the memory device is in the test mode to perform a test mode operation.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: February 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Michael R. Spica, David G. Springberg
  • Publication number: 20230025355
    Abstract: A memory sub-system comprises a power management component comprising a plurality of regulators configured to supply respective operating voltages for components of the memory sub-system. The power management component is configured to adjust a regulator voltage level provided to a particular component until an operation state change of the particular component is detected. The power management voltage level is further configured to determine a value of the regulator voltage level at which the operation state change of the particular component is detected.
    Type: Application
    Filed: October 7, 2022
    Publication date: January 26, 2023
    Inventors: Michael R. Spica, Patrick T. Caraher
  • Publication number: 20220382348
    Abstract: A system receives event information associated with an event that corresponds to a temperature of a memory sub-system including memory devices encased in respective packages. The system determines whether the event information associated with the event satisfies a threshold condition. Responsive to determining that the event information associated with the event satisfies the threshold condition, the system causes a thermoelectric component (TEC) that is coupled to an external surface of each of the respective packages of the memory devices of the memory sub-system to transfer thermal energy between the TEC and the memory devices via thermal conduction.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventor: Michael R. Spica
  • Patent number: 11474888
    Abstract: A memory sub-system comprises a power management component comprising a plurality of regulators configured to supply respective operating voltages for components of the memory sub-system. The power management component is configured to adjust a regulator voltage level provided to a particular component until an operation state change of the particular component is detected. The power management voltage level is further configured to determine a value of the regulator voltage level at which the operation state change of the particular component is detected.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: October 18, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Michael R. Spica, Patrick T. Caraher
  • Patent number: 11416048
    Abstract: First event information that is associated with an event that corresponds to a temperature of a memory sub-system is received. Whether the first event information associated with the event that corresponds to the temperature of the memory sub-system satisfies a first threshold condition is determined. Responsive to determining that the first event information associated with the event that corresponds to the temperature of the memory sub-system satisfies the first threshold condition, a thermoelectric component (TEC) is caused to change from an inactive state to an active state by decreasing a temperature at a bottom surface of the TEC that is coupled to the memory sub-system as a temperature at a top surface of the TEC increases.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Michael R. Spica
  • Publication number: 20220230700
    Abstract: A detection is made by a processing device allocated to a memory device test board of a distributed test platform that a memory sub-system has engaged with a memory device test resource of the memory device test board. A test is identified to be performed for a memory device of the memory sub-system. The test includes first instructions to be executed by a memory sub-system controller of the memory sub-system in performance of the test and second instructions to be executed by the processing device in performance of the test. The second instructions are to cause one or more test condition components of the memory device test resource to generate one or more test conditions to be applied to the memory device while the memory sub-system executes the first instructions. Responsive to a transmission of the first instructions to the memory sub-system controller, the second instructions are executed.
    Type: Application
    Filed: April 8, 2022
    Publication date: July 21, 2022
    Inventors: Gary D. Hamor, Michael R. Spica, Donald Shepard, Patrick Caraher, João Elmiro da Rocha Chaves
  • Patent number: 11328789
    Abstract: A test rack includes two or more memory device test boards where each memory device test boards includes two or more memory device test resources. Each of the two or more memory device test boards includes a separate processing device allocated to the memory device test resources of a corresponding memory device test boards. A processing device of a test board detects that a first memory sub-system has engaged with a first memory device test resource of the corresponding memory device test board. The processing device identifies a first test to be performed for a first memory device of the first memory sub-system, where the first test includes one or more first test instructions to be executed in performance of the first test. The processing device causes the one or more first test instructions to be transmitted to the first memory sub-system, where the first test is performed by the one or more first test instructions executing at the first memory sub-system.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: May 10, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Gary D. Hamor, Michael R. Spica, Donald Shepard, Patrick Caraher, João Elmiro da Rocha Chaves
  • Publication number: 20220044750
    Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device is configured to switch an operating mode of the memory device between a test mode and a non-test mode. The system further includes a test mode access component that is configured to access the memory device while the memory device is in the test mode to perform a test mode operation.
    Type: Application
    Filed: August 6, 2020
    Publication date: February 10, 2022
    Inventors: Michael R. Spica, David G. Springberg
  • Publication number: 20210224147
    Abstract: A memory sub-system comprises a power management component comprising a plurality of regulators configured to supply respective operating voltages for components of the memory sub-system. The power management component is configured to adjust a regulator voltage level provided to a particular component until an operation state change of the particular component is detected. The power management voltage level is further configured to determine a value of the regulator voltage level at which the operation state change of the particular component is detected.
    Type: Application
    Filed: April 2, 2021
    Publication date: July 22, 2021
    Inventors: Michael R. Spica, Patrick T. Caraher
  • Publication number: 20210193250
    Abstract: A test rack includes two or more memory device test boards where each memory device test boards includes two or more memory device test resources. Each of the two or more memory device test boards includes a separate processing device allocated to the memory device test resources of a corresponding memory device test boards. A processing device of a test board detects that a first memory sub-system has engaged with a first memory device test resource of the corresponding memory device test board. The processing device identifies a first test to be performed for a first memory device of the first memory sub-system, where the first test includes one or more first test instructions to be executed in performance of the first test. The processing device causes the one or more first test instructions to be transmitted to the first memory sub-system, where the first test is performed by the one or more first test instructions executing at the first memory sub-system.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 24, 2021
    Inventors: Gary D. Hamor, Michael R. Spica, Donald Shepard, Patrick Caraher, João Elmiro da Rocha Chaves
  • Patent number: 10983852
    Abstract: A memory sub-system comprises a power management component comprising a plurality of regulators configured to supply respective operating voltages for components of the memory sub-system. The power management component is configured to adjust a regulator voltage level provided to a particular component until an operation state change of the particular component is detected. The power management voltage level is further configured to determine a value of the regulator voltage level at which the operation state change of the particular component is detected.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: April 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Michael R. Spica, Patrick T. Caraher
  • Publication number: 20210026425
    Abstract: First event information that is associated with an event that corresponds to a temperature of a memory sub-system is received. Whether the first event information associated with the event that corresponds to the temperature of the memory sub-system satisfies a first threshold condition is determined. Responsive to determining that the first event information associated with the event that corresponds to the temperature of the memory sub-system satisfies the first threshold condition, a thermoelectric component (TEC) is caused to change from an inactive state to an active state by decreasing a temperature at a bottom surface of the TEC that is coupled to the memory sub-system as a temperature at a top surface of the TEC increases.
    Type: Application
    Filed: July 22, 2019
    Publication date: January 28, 2021
    Inventor: Michael R. Spica
  • Publication number: 20200243119
    Abstract: A memory sub-system comprises a power management component comprising a plurality of regulators configured to supply respective operating voltages for components of the memory sub-system. The power management component is configured to adjust a regulator voltage level provided to a particular component until an operation state change of the particular component is detected. The power management voltage level is further configured to determine a value of the regulator voltage level at which the operation state change of the particular component is detected.
    Type: Application
    Filed: January 30, 2019
    Publication date: July 30, 2020
    Inventors: Michael R. Spica, Patrick T. Caraher