Patents by Inventor Michael R. Spica
Michael R. Spica has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11960349Abstract: A memory sub-system comprises a power management component comprising a plurality of regulators configured to supply respective operating voltages for components of the memory sub-system. The power management component is configured to adjust a regulator voltage level provided to a particular component until an operation state change of the particular component is detected. The power management voltage level is further configured to determine a value of the regulator voltage level at which the operation state change of the particular component is detected.Type: GrantFiled: October 7, 2022Date of Patent: April 16, 2024Assignee: Micron Technology, Inc.Inventors: Michael R. Spica, Patrick T. Caraher
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Patent number: 11854637Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device is configured to switch an operating mode of the memory device between a test mode and a non-test mode. The system further includes a test mode access component that is configured to access the memory device while the memory device is in the test mode to perform a test mode operation.Type: GrantFiled: January 31, 2023Date of Patent: December 26, 2023Assignee: Micron Technology, Inc.Inventors: Michael R. Spica, David G. Springberg
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Publication number: 20230178163Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device is configured to switch an operating mode of the memory device between a test mode and a non-test mode. The system further includes a test mode access component that is configured to access the memory device while the memory device is in the test mode to perform a test mode operation.Type: ApplicationFiled: January 31, 2023Publication date: June 8, 2023Inventors: Michael R. Spica, David G. Springberg
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Patent number: 11581053Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device is configured to switch an operating mode of the memory device between a test mode and a non-test mode. The system further includes a test mode access component that is configured to access the memory device while the memory device is in the test mode to perform a test mode operation.Type: GrantFiled: August 6, 2020Date of Patent: February 14, 2023Assignee: Micron Technology, Inc.Inventors: Michael R. Spica, David G. Springberg
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Publication number: 20230025355Abstract: A memory sub-system comprises a power management component comprising a plurality of regulators configured to supply respective operating voltages for components of the memory sub-system. The power management component is configured to adjust a regulator voltage level provided to a particular component until an operation state change of the particular component is detected. The power management voltage level is further configured to determine a value of the regulator voltage level at which the operation state change of the particular component is detected.Type: ApplicationFiled: October 7, 2022Publication date: January 26, 2023Inventors: Michael R. Spica, Patrick T. Caraher
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Publication number: 20220382348Abstract: A system receives event information associated with an event that corresponds to a temperature of a memory sub-system including memory devices encased in respective packages. The system determines whether the event information associated with the event satisfies a threshold condition. Responsive to determining that the event information associated with the event satisfies the threshold condition, the system causes a thermoelectric component (TEC) that is coupled to an external surface of each of the respective packages of the memory devices of the memory sub-system to transfer thermal energy between the TEC and the memory devices via thermal conduction.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Inventor: Michael R. Spica
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Patent number: 11474888Abstract: A memory sub-system comprises a power management component comprising a plurality of regulators configured to supply respective operating voltages for components of the memory sub-system. The power management component is configured to adjust a regulator voltage level provided to a particular component until an operation state change of the particular component is detected. The power management voltage level is further configured to determine a value of the regulator voltage level at which the operation state change of the particular component is detected.Type: GrantFiled: April 2, 2021Date of Patent: October 18, 2022Assignee: Micron Technology, Inc.Inventors: Michael R. Spica, Patrick T. Caraher
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Patent number: 11416048Abstract: First event information that is associated with an event that corresponds to a temperature of a memory sub-system is received. Whether the first event information associated with the event that corresponds to the temperature of the memory sub-system satisfies a first threshold condition is determined. Responsive to determining that the first event information associated with the event that corresponds to the temperature of the memory sub-system satisfies the first threshold condition, a thermoelectric component (TEC) is caused to change from an inactive state to an active state by decreasing a temperature at a bottom surface of the TEC that is coupled to the memory sub-system as a temperature at a top surface of the TEC increases.Type: GrantFiled: July 22, 2019Date of Patent: August 16, 2022Assignee: Micron Technology, Inc.Inventor: Michael R. Spica
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Publication number: 20220230700Abstract: A detection is made by a processing device allocated to a memory device test board of a distributed test platform that a memory sub-system has engaged with a memory device test resource of the memory device test board. A test is identified to be performed for a memory device of the memory sub-system. The test includes first instructions to be executed by a memory sub-system controller of the memory sub-system in performance of the test and second instructions to be executed by the processing device in performance of the test. The second instructions are to cause one or more test condition components of the memory device test resource to generate one or more test conditions to be applied to the memory device while the memory sub-system executes the first instructions. Responsive to a transmission of the first instructions to the memory sub-system controller, the second instructions are executed.Type: ApplicationFiled: April 8, 2022Publication date: July 21, 2022Inventors: Gary D. Hamor, Michael R. Spica, Donald Shepard, Patrick Caraher, João Elmiro da Rocha Chaves
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Patent number: 11328789Abstract: A test rack includes two or more memory device test boards where each memory device test boards includes two or more memory device test resources. Each of the two or more memory device test boards includes a separate processing device allocated to the memory device test resources of a corresponding memory device test boards. A processing device of a test board detects that a first memory sub-system has engaged with a first memory device test resource of the corresponding memory device test board. The processing device identifies a first test to be performed for a first memory device of the first memory sub-system, where the first test includes one or more first test instructions to be executed in performance of the first test. The processing device causes the one or more first test instructions to be transmitted to the first memory sub-system, where the first test is performed by the one or more first test instructions executing at the first memory sub-system.Type: GrantFiled: December 18, 2019Date of Patent: May 10, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Gary D. Hamor, Michael R. Spica, Donald Shepard, Patrick Caraher, João Elmiro da Rocha Chaves
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Publication number: 20220044750Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device is configured to switch an operating mode of the memory device between a test mode and a non-test mode. The system further includes a test mode access component that is configured to access the memory device while the memory device is in the test mode to perform a test mode operation.Type: ApplicationFiled: August 6, 2020Publication date: February 10, 2022Inventors: Michael R. Spica, David G. Springberg
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Publication number: 20210224147Abstract: A memory sub-system comprises a power management component comprising a plurality of regulators configured to supply respective operating voltages for components of the memory sub-system. The power management component is configured to adjust a regulator voltage level provided to a particular component until an operation state change of the particular component is detected. The power management voltage level is further configured to determine a value of the regulator voltage level at which the operation state change of the particular component is detected.Type: ApplicationFiled: April 2, 2021Publication date: July 22, 2021Inventors: Michael R. Spica, Patrick T. Caraher
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Publication number: 20210193250Abstract: A test rack includes two or more memory device test boards where each memory device test boards includes two or more memory device test resources. Each of the two or more memory device test boards includes a separate processing device allocated to the memory device test resources of a corresponding memory device test boards. A processing device of a test board detects that a first memory sub-system has engaged with a first memory device test resource of the corresponding memory device test board. The processing device identifies a first test to be performed for a first memory device of the first memory sub-system, where the first test includes one or more first test instructions to be executed in performance of the first test. The processing device causes the one or more first test instructions to be transmitted to the first memory sub-system, where the first test is performed by the one or more first test instructions executing at the first memory sub-system.Type: ApplicationFiled: December 18, 2019Publication date: June 24, 2021Inventors: Gary D. Hamor, Michael R. Spica, Donald Shepard, Patrick Caraher, João Elmiro da Rocha Chaves
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Patent number: 10983852Abstract: A memory sub-system comprises a power management component comprising a plurality of regulators configured to supply respective operating voltages for components of the memory sub-system. The power management component is configured to adjust a regulator voltage level provided to a particular component until an operation state change of the particular component is detected. The power management voltage level is further configured to determine a value of the regulator voltage level at which the operation state change of the particular component is detected.Type: GrantFiled: January 30, 2019Date of Patent: April 20, 2021Assignee: Micron Technology, Inc.Inventors: Michael R. Spica, Patrick T. Caraher
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Publication number: 20210026425Abstract: First event information that is associated with an event that corresponds to a temperature of a memory sub-system is received. Whether the first event information associated with the event that corresponds to the temperature of the memory sub-system satisfies a first threshold condition is determined. Responsive to determining that the first event information associated with the event that corresponds to the temperature of the memory sub-system satisfies the first threshold condition, a thermoelectric component (TEC) is caused to change from an inactive state to an active state by decreasing a temperature at a bottom surface of the TEC that is coupled to the memory sub-system as a temperature at a top surface of the TEC increases.Type: ApplicationFiled: July 22, 2019Publication date: January 28, 2021Inventor: Michael R. Spica
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Publication number: 20200243119Abstract: A memory sub-system comprises a power management component comprising a plurality of regulators configured to supply respective operating voltages for components of the memory sub-system. The power management component is configured to adjust a regulator voltage level provided to a particular component until an operation state change of the particular component is detected. The power management voltage level is further configured to determine a value of the regulator voltage level at which the operation state change of the particular component is detected.Type: ApplicationFiled: January 30, 2019Publication date: July 30, 2020Inventors: Michael R. Spica, Patrick T. Caraher
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Patent number: 6757209Abstract: An apparatus and method for testing memory cells comprising coupling a first and a second memory cell to a first and a second bit lines, respectively, reading data from the first and second memory cells through the first and second bit lines, and comparing the voltage levels of the first and second bit lines.Type: GrantFiled: March 30, 2001Date of Patent: June 29, 2004Assignee: Intel CorporationInventors: Tak M. Mak, Michael R. Spica, Michael J. Tripp
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Patent number: 6721216Abstract: An apparatus and method for testing an address decoder and word lines of a memory array comprised of connecting a signature analyzer to the word lines emanating from an address decoder, setting a clock used to trigger the latching of the states of the word lines by the signature analyzer, transmitting an address to the address decoder to be decoded, and triggering the signature analyzer to latch the state of the word lines.Type: GrantFiled: March 30, 2001Date of Patent: April 13, 2004Assignee: Intel CorporationInventors: Tak M. Mak, Michael R. Spica, Michael J. Tripp
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Publication number: 20020141276Abstract: An apparatus and method for testing an address decoder and word lines of a memory array comprised of connecting a signature analyzer to the word lines emanating from an address decoder, setting a clock used to trigger the latching of the states of the word lines by the signature analyzer, transmitting an address to the address decoder to be decoded, and triggering the signature analyzer to latch the state of the word lines.Type: ApplicationFiled: March 30, 2001Publication date: October 3, 2002Inventors: Tak M. Mak, Michael R. Spica, Michael J. Tripp
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Publication number: 20020141259Abstract: An apparatus and method for testing memory cells comprising coupling a first and a second memory cell to a first and a second bit lines, respectively, reading data from the first and second memory cells through the first and second bit lines, and comparing the voltage levels of the first and second bit lines.Type: ApplicationFiled: March 30, 2001Publication date: October 3, 2002Inventors: Tak M. Mak, Michael R. Spica, Michael J. Tripp