Abstract: A multiprocessor computer includes a planar board and a processor card mounted on the planar board. An interrupt controller is mounted on the planar board and has a plurality of interrupt input lines for receiving interrupt requests from a plurality of interrupting devices. The interrupt controller also has an output line that transmits an interrupt to the processor card. The processor card includes an interrupt director having a plurality of interrupt request lines respectively connected to interrupt request pins of the different processors. The director is also connected to the output line coming from the interrupt controller. In response to receiving an interrupt request from the interrupt controller, the director performs an interrupt acknowledge cycle and transmits an interrupt request, on only one of the interrupt request lines, to a specific processor predetermined by the director. The specific processor then reads an interrupt vector from the director.

Abstract: System non-maskable interrupts are detected by an override controller which initiates an NMI routine override operation. During override, address requests for an standard NMI routine are intercepted, and instead a predetermined memory space is addressed that contains a system specific NMI trace routine. The processor is unaware that the override controller has inserted the system specific NMI routines. The processor executes the system specific NMI routines, and when the specific routines are completed, the override controller generates a termination signal which returns program control back to the standard NMI routine. The system specific NMI routine is designed to trace errors created by new system functions or hardware or to enhance the error tracing capability for existing system functions.

Abstract: A hardware-based system for managing multiple input/output devices sharing the same set of addresses in a computer system is described. The new VIRTUAL ENABLED state is a hybrid of the current ENABLED or ACTIVE and DISABLED or INACTIVE states. In the ENABLED state, an input/output (I/O) adapter responds to I/O addressing and presents interrupts to the processor. In the DISABLED state, the I/O adapter does not respond to I/O addressing and does not present interrupts. In the new VIRTUAL ENABLED state, the adapter does not respond to I/O addressing (as in the DISABLED state), but will still produce an interrupt (as in the ENABLED state). With the VIRTUAL state, multiple I/O adapters that would normally content for the same set of addresses (ENABLED state), or optionally be rendered inoperable (DISABLED state), can always remain available for I/O. A single register where the processor can read the interrupt status for all ENABLED and/or VIRTUAL ENABLED adapters sharing the same set of addresses is provided.

Abstract: Apparatus and procedure for accurately positioning and magnetically holding a flexible ferrous plate on the surface of a rotary printing cylinder. Movable registering pins and a permanent bar magnet are mounted to the rotary cylinder and controlled by a single operating means. The pins and magnetic bar are alternately moved toward and away from the cylinder surface such that, when the pins are initially projected to register with positioning holes in the plate, the magnet is withdrawn. When the pins are withdrawn the magnet is simultaneously advanced to "grab" the leading edge of the plate. The operating means is controlled by a foot pedal linkage. The trailing edge of the plate is held in position by a second bar magnet. To remove the plate, the procedure is reversed so as to simultaneously advance the register pins and retract the bar magnet to release the leading edge of the plate.

Abstract: A system is disclosed for managing a plurality of interrupt handlers in a linked-list data structure, for servicing a plurality of input/output devices sharing a common interrupt line in a microcomputer. The system provides for an orderly method to link a newly loaded interrupt handler routine into a linked-list data structure consisting of previously loaded interrupt handler routines. The system further provides for an orderly method to share a common interrupt line among a plurality of input/output devices being serviced by the interrupt handlers. The system further provides for an orderly means to unlink a particular interrupt handler routine from the linked-list data structure when a corresponding input/output device is to be deactivated. The system finds special utility in a multitasking operating system environment where input/output devices can be deactivated in a different sequence from that in which they were originally activated.