Abstract: A computer interconnect system uses packet data transmission over serial links connecting nodes of a network. The serial links provide simultaneous dual paths for transmit/receive. An adapter couples a CPU or the like at a node to the serial link. The adapter includes a packet memory for temporarily storing transmit packets and receive packets, along with a port processor for executing the protocol. The packet memory includes two zones in which the received packets are stored interchangably. Packets of data are transferred between the system bus of the CPU and the packet memory by a pair of data movers, one for read and one for write. The packet memory is accessed upon demand by the serial link, the port processor and the data movers, using interleaved cycles. The order of buffering the received packets in the two zones is recorded in a file or silo, and when the packets are transferred to the CPU the packets are accessed by referring to this silo so the order of receipt is maintained.