Patents by Inventor Michael Ray Sievers
Michael Ray Sievers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140145189Abstract: Technologies generally described herein relate to multilayer circuit boards with optical vias for data transmission between the layers. One or more regions may be created on a multilayer circuit board for optical vias. A transparent conducting oxide (TCO) layer can be deposited on a top and/or bottom layer of the circuit board. P-N junctions can be created over the TCO layer about the one or more regions to form optical vias as photo-emitting and/or photo-detecting components. The photo-emitting and/or photo-detecting components may be coupled to electronic components on the multilayer circuit board.Type: ApplicationFiled: January 30, 2014Publication date: May 29, 2014Applicant: Empire Technology Development, LLCInventor: Michael Ray Sievers
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Patent number: 8492295Abstract: A semiconductor structure fabrication method. A provided structure includes: a semiconductor substrate, a transistor on the semiconductor substrate, N interconnect layers on the semiconductor substrate, and a temporary filling region within the N layers. N is at least 2. The temporary filling region is heated at a high temperature sufficiently high to result in the temporary filling material being replaced by a cooling pipes system that does not include any solid or liquid material. A first portion and a second portion of the cooling pipes system are each in direct physical contact with a surrounding ambient at a first interface and a second interface respectively such that a first direction perpendicular to the first interface is perpendicular to a second direction perpendicular to the second interface. A totality of interfaces between the cooling pipes system and the ambient consists of the first interface and the second interface.Type: GrantFiled: September 13, 2012Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Kaushik A. Kumar, Andres Fernando Munoz, Michael Ray Sievers, Richard Stephen Wise
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Publication number: 20130012018Abstract: A semiconductor structure fabrication method. A provided structure includes: a semiconductor substrate, a transistor on the semiconductor substrate, N interconnect layers on the semiconductor substrate, and a temporary filling region within the N layers. N is at least 2. The temporary filling region is heated at a high temperature sufficiently high to result in the temporary filling material being replaced by a cooling pipes system that does not include any solid or liquid material. A first portion and a second portion of the cooling pipes system are each in direct physical contact with a surrounding ambient at a first interface and a second interface respectively such that a first direction perpendicular to the first interface is perpendicular to a second direction perpendicular to the second interface. A totality of interfaces between the cooling pipes system and the ambient consists of the first interface and the second interface.Type: ApplicationFiled: September 13, 2012Publication date: January 10, 2013Applicant: International Business Machines CorporationInventors: Kaushik A. Kumar, Andres Fernando Munoz, Michael Ray Sievers, Richard Stephen Wise
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Patent number: 8298966Abstract: Structures and methods for forming the same. A semiconductor chip includes a substrate and a transistor. The chip includes N interconnect layers on the substrate, N being a positive integer. The chip includes a cooling pipes system inside the N interconnect layers. The cooling pipes system does not include any solid or liquid material. Given any first point and any second point in the cooling pipes system, there exists a continuous path which connects the first and second points and which is totally within the cooling pipes system. A first portion of the cooling pipes system overlaps the transistor. A second portion of the cooling pipes system is higher than the substrate and lower than a top interconnect layer. The second portion is in direct physical contact with a surrounding ambient.Type: GrantFiled: February 2, 2010Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Kaushik A. Kumar, Andres Fernando Munoz, Michael Ray Sievers, Richard Stephen Wise
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Publication number: 20100136800Abstract: Structures and methods for forming the same. A semiconductor chip includes a substrate and a transistor. The chip includes N interconnect layers on the substrate, N being a positive integer. The chip includes a cooling pipes system inside the N interconnect layers. The cooling pipes system does not include any solid or liquid material. Given any first point and any second point in the cooling pipes system, there exists a continuous path which connects the first and second points and which is totally within the cooling pipes system. A first portion of the cooling pipes system overlaps the transistor. A second portion of the cooling pipes system is higher than the substrate and lower than a top interconnect layer. The second portion is in direct physical contact with a surrounding ambient.Type: ApplicationFiled: February 2, 2010Publication date: June 3, 2010Applicant: International Business Machines CorporationInventors: Kaushik A. Kumar, Andres Fernando Munoz, Michael Ray Sievers, Richard Stephen Wise
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Patent number: 7659616Abstract: Structures and methods for forming the same. A semiconductor chip includes a substrate and a transistor. The chip includes N interconnect layers on the substrate, N being a positive integer. The chip includes a cooling pipes system inside the N interconnect layers. The cooling pipes system does not include any solid or liquid material. Given any first point and any second point in the cooling pipes system, there exists a continuous path which connects the first and second points and which is totally within the cooling pipes system. A first portion of the cooling pipes system overlaps the transistor. A second portion of the cooling pipes system is higher than the substrate and lower than a top interconnect layer. The second portion is in direct physical contact with a surrounding ambient.Type: GrantFiled: October 10, 2007Date of Patent: February 9, 2010Assignee: International Business Machines CorporationInventors: Kaushik A. Kumar, Andres Fernando Munoz, Michael Ray Sievers, Richard Stephen Wise
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Publication number: 20090096056Abstract: Structures and methods for forming the same. A semiconductor chip includes a substrate and a transistor. The chip includes N interconnect layers on the substrate, N being a positive integer. The chip includes a cooling pipes system inside the N interconnect layers. The cooling pipes system does not include any solid or liquid material. Given any first point and any second point in the cooling pipes system, there exists a continuous path which connects the first and second points and which is totally within the cooling pipes system. A first portion of the cooling pipes system overlaps the transistor. A second portion of the cooling pipes system is higher than the substrate and lower than a top interconnect layer. The second portion is in direct physical contact with a surrounding ambient.Type: ApplicationFiled: October 10, 2007Publication date: April 16, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kaushik A. Kumar, Andres Fernando Munoz, Michael Ray Sievers, Richard Stephen Wise
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Publication number: 20040132287Abstract: A method of focused ion beam milling of a copper on a sample, and a focused ion beam apparatus. The method comprises the steps of exposing an area of copper on the sample; and forming a given feature in the copper area by using the focused ion beam to draw a mill box in the copper area, scanning the focused ion beam across the mill box for an extended period of time to remove a portion of the copper in the copper area and thereby to form the given feature, and introducing tetramethylcyclotetrasiloxane (TMCTS) in said area during the scanning step. After the copper feature is formed, a very light dose of XeF2 may be introduced to clean up any residue that may have formed.Type: ApplicationFiled: January 7, 2003Publication date: July 8, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence S. Fischer, Steven Brett Herschbein, Chad Rue, Carmelo F. Scrudato, Michael Ray Sievers