Abstract: A stacked processor-plus-memory device includes a processing die with an array of processing elements of an artificial neural network. Each processing element multiplies a first operand—e.g. a weight—by a second operand to produce a partial result to a subsequent processing element. To prepare for these computations, a sequencer loads the weights into the processing elements as a sequence of operands that step through the processing elements, each operand stored in the corresponding processing element. The operands can be sequenced directly from memory to the processing elements or can be stored first in cache. The processing elements include streaming logic that disregards interruptions in the stream of operands.

Abstract: A device includes a memory controller and a cache memory coupled to the memory controller. The cache memory has a first set of cache lines associated with a first memory block and comprising a first plurality of cache storage locations, as well as a second set of cache lines associated with a second memory block and comprising a second plurality of cache storage locations. A first location of the second plurality of cache storage locations comprises cache tag data for both the first set of cache lines and the second set of cache lines.

Abstract: Disclosed is a dynamic random access memory that has columns, data rows, tag rows and comparators. Each comparator compares address bits and tag information bits from the tag rows to determine a cache hit and generate address bits to access data information in the DRAM as a multiway set associative cache.

Abstract: Reducing power consumption in latches and similar electronic devices. In one aspect, an apparatus for configuring power consumption of sequential logic includes a sequential logic device including a first latch, a second latch, and first and second enable inputs. The first enable input enables and disables the first and second latches, and the second enable input enables and disables the second latch and does not affect the first latch. The first enable input has an earlier required signal arrival time than the second enable input to be effective for a particular clock cycle. A circuit configures the sequential logic device at operating time to consume less power during a lower frequency of operation of the sequential logic device, and to consume more power during a higher frequency of operation.

Abstract: Reducing power consumption in latches and similar electronic devices. In one aspect, an apparatus for configuring power consumption of sequential logic includes a sequential logic device including a first latch, a second latch, and first and second enable inputs. The first enable input enables and disables the first and second latches, and the second enable input enables and disables the second latch and does not affect the first latch. The first enable input has an earlier required signal arrival time than the second enable input to be effective for a particular clock cycle. A circuit configures the sequential logic device at operating time to consume less power during a lower frequency of operation of the sequential logic device, and to consume more power during a higher frequency of operation.

Abstract: Reducing power consumption in latches and similar electronic devices. In one aspect, an apparatus for configuring power consumption of sequential logic includes a sequential logic device including a first latch, a second latch, and first and second enable inputs. The first enable input enables and disables the first and second latches, and the second enable input enables and disables the second latch and does not affect the first latch. The first enable input has an earlier required signal arrival time than the second enable input to be effective for a particular clock cycle. A circuit configures the sequential logic device at operating time to consume less power during a lower frequency of operation of the sequential logic device, and to consume more power during a higher frequency of operation.

Abstract: The present invention provides a method and system for fixed length bursts of data on a bus within a data processing system. The method and system in accordance with the present invention provides a burst transfer protocol which includes the providing of length information of a fixed length burst of data on a signal from at least one master device to at least one slave device when the at least one master device requests the fixed length burst of data. It also includes the asserting of a burst termination signal by the at least one slave device one cycle prior to a last cycle in the fixed length burst, and the asserting of a burst complete signal during the last cycle in the fixed length burst for a write burst, or one cycle prior to the last cycle in the fixed length burst for a read burst, based on the value of the signal. This burst transfer protocol enables burst transfers of a maximum length to be performed across a local bus between a master and a slave without dead cycle penalties after the transfer.