Abstract: Error detection or correction is provided on the same chip as DRAM memory. Because data and error correction bits need not travel on an external bus, error detection/correction can be conducted on a larger number of bits than the width of the data bus. When using memories which provide for access to a row of memory, such as static-column or fast-page mode memories, error correction is conducted on an entire row of memory during one error correction cycle. Following operations of the correction cycle, the data within a row of memory can be accessed independently of the EC circuitry.