Abstract: A method is provided of forming a superconductor device interconnect structure. The method includes forming a first dielectric layer overlying a substrate, and forming a superconducting interconnect element in a first dielectric layer, such that the superconducting interconnect element has a top surface aligned with a top surface of the first dielectric layer to form a first interconnect layer. The method also includes performing a plasma clean on a top surface of the first interconnect layer, and depositing a second dielectric layer over the first dielectric layer.

Abstract: A method is provided of forming a bipolar transistor device. The method comprises depositing a collector dielectric layer over a substrate in a collector active region, depositing a dielectric anti-reflective (DARC) layer over the collector dielectric layer, dry etching away a base opening in the DARC layer, and wet etching away a portion of the collector dielectric layer in the base opening to provide an extended base opening to the substrate. The method further comprises performing a base deposition to form a base epitaxy region in the extended base opening and extending over first and second portions of the DARC layer that remains as a result of the dry etching away the base opening in the DARC layer, and forming an emitter region over the base epitaxy region.

Abstract: A method is provided of forming a bipolar transistor device. The method comprises depositing a collector dielectric layer over a substrate in a collector active region, depositing a dielectric anti-reflective (DARC) layer over the collector dielectric layer, dry etching away a base opening in the DARC layer, and wet etching away a portion of the collector dielectric layer in the base opening to provide an extended base opening to the substrate. The method further comprises performing a base deposition to form a base epitaxy region in the extended base opening and extending over first and second portions of the DARC layer that remains as a result of the dry etching away the base opening in the DARC layer, and forming an emitter region over the base epitaxy region.

Abstract: A method is provided of forming a superconductor device interconnect structure. The method includes forming a first dielectric layer overlying a substrate, and forming a base electrode in the first dielectric layer with the base electrode having a top surface aligned with the top surface of the first dielectric layer. The method further comprises forming a Josephson junction (JJ) over the base electrode, depositing a second dielectric layer over the JJ, the base electrode and the first dielectric layer, and forming a first contact through the second dielectric layer to the base electrode to electrically couple the first contact to a first end of the JJ, and a second contact through the second dielectric layer to a second end of the JJ.

Abstract: A media transport module comprising: a transport extending from a pick coupling area to a stacking port; and a retractable guide. The retractable guide is moveable to extend beyond the stacking port when media items are being stacked and thereby guide media items ejected from the stacking port onto a carriage plate. The retractable guide is also moveable to retract to the stacking port when media items have been stacked so that the carriage plate can close without touching the retractable guide.

Abstract: A method is provided of forming a bipolar transistor device. The method comprises depositing a collector dielectric layer over a substrate in a collector active region, depositing a dielectric anti-reflective (DARC) layer over the collector dielectric layer, dry etching away a base opening in the DARC layer, and wet etching away a portion of the collector dielectric layer in the base opening to provide an extended base opening to the substrate. The method further comprises performing a base deposition to form a base epitaxy region in the extended base opening and extending over first and second portions of the DARC layer that remains as a result of the dry etching away the base opening in the DARC layer, and forming an emitter region over the base epitaxy region.

Abstract: A method is provided of forming a bipolar transistor device. The method comprises depositing a collector dielectric layer over a substrate in a collector active region, depositing a dielectric anti-reflective (DARC) layer over the collector dielectric layer, dry etching away a base opening in the DARC layer, and wet etching away a portion of the collector dielectric layer in the base opening to provide an extended base opening to the substrate. The method further comprises performing a base deposition to form a base epitaxy region in the extended base opening and extending over first and second portions of the DARC layer that remains as a result of the dry etching away the base opening in the DARC layer, and forming an emitter region over the base epitaxy region.

Abstract: A method is provided of forming a bipolar transistor device. The method comprises depositing a collector dielectric layer over a substrate in a collector active region, depositing a dielectric anti-reflective (DARC) layer over the collector dielectric layer, dry etching away a base opening in the DARC layer, and wet etching away a portion of the collector dielectric layer in the base opening to provide an extended base opening to the substrate. The method further comprises performing a base deposition to form a base epitaxy region in the extended base opening and extending over first and second portions of the DARC layer that remains as a result of the dry etching away the base opening in the DARC layer, and forming an emitter region over the base epitaxy region.

Abstract: A removable media container for use in a media dispenser is described. The media container comprises: a diverter entrance for receiving diverted media items prior to stacking of the media items; a non-present stack entrance for receiving a stack of media items subsequent to stacking of the media items but prior to presentation of the stack of media items to a customer; and a present stack entrance for receiving a stack of media items subsequent to presentation of the stack of media items to a customer.

Abstract: Methods are provided for forming a capacitor. In one embodiment, a method comprises providing an insulator material layer over a substrate, etching at least one via in the insulator material layer and depositing a contact material fill in the at least one via to form a first set of contacts. The method further comprises etching the insulator material layer adjacent at least one contact of the first set of contacts to form at least one void, depositing a dielectric material layer over the at least one void and over the first set of contacts and depositing a contact material fill in the at least void to form a second set of contacts.

Abstract: A removable media container for use in a media dispenser is described. The media container comprises: a diverter entrance for receiving diverted media items prior to stacking of the media items; a non-present stack entrance for receiving a stack of media items subsequent to stacking of the media items but prior to presentation of the stack of media items to a customer; and a present stack entrance for receiving a stack of media items subsequent to presentation of the stack of media items to a customer.

Abstract: An embodiment of a method is disclosed to integrate silicon oxide nitride oxide silicon (SONOS) non-volatile memory (NVM) into a standard sub-90 nm complementary metal oxide semiconductor (CMOS) semiconductor foundry process flow. An embodiment of the method adds a few additional steps to a standard CMOS foundry process flow and makes minor changes to the rest of the baseline CMOS foundry process flow to form a new process module that includes both CMOS devices and an embedded SONOS NVM. An embodiment of the method utilizes new material sets (which are not utilized at larger nodes) that enhance NVM performance by improving charge tunneling behavior and reducing leakage currents. Furthermore, an embodiment of the method integrates CMOS with SONOS NVM at ever-shrinking dimensions while enhancing the NVM performance, without performing extra, costly processing steps.

Abstract: Methods are provided for forming a capacitor. In one embodiment, a method comprises providing an insulator material layer over a substrate, etching at least one via in the insulator material layer and depositing a contact material fill in the at least one via to form a first set of contacts. The method further comprises etching the insulator material layer adjacent at least one contact of the first set of contacts to form at least one void, depositing a dielectric material layer over the at least one void and over the first set of contacts and depositing a contact material fill in the at least void to form a second set of contacts.

Abstract: A media presenter is described. The media presenter comprises: a chassis including a central track; a nose coupled to the chassis at a nose end of the chassis; and a carriage. The nose includes a presenting end distal from the chassis, and a nose track arranged to couple to the central track to provide a presenting track extending from the chassis to the presenting end. The carriage is mounted on the presenting track for movement therealong, and comprises a carriage body and a carriage plate movable between an open position at which media items can be placed on the carriage plate, and a closed position for clamping media items between the carriage plate and the carriage body.

Abstract: A media transport module comprising: a transport extending from a pick coupling area to a stacking port; and a retractable guide. The retractable guide is moveable to extend beyond the stacking port when media items are being stacked and thereby guide media items ejected from the stacking port onto a carriage plate. The retractable guide is also moveable to retract to the stacking port when media items have been stacked so that the carriage plate can close without touching the retractable guide.

Abstract: A media presenter is described. The media presenter comprises: a chassis including a central track; a nose coupled to the chassis at a nose end of the chassis; and a carriage. The nose includes a presenting end distal from the chassis, and a nose track arranged to couple to the central track to provide a presenting track extending from the chassis to the presenting end. The carriage is mounted on the presenting track for movement therealong, and comprises a carriage body and a carriage plate movable between an open position at which media items can be placed on the carriage plate, and a closed position for clamping media items between the carriage plate and the carriage body.

Abstract: A removable media container for use in a media dispenser is described. The media container comprises: a diverter entrance for receiving diverted media items prior to stacking of the media items; a non-present stack entrance for receiving a stack of media items subsequent to stacking of the media items but prior to presentation of the stack of media items to a customer; and a present stack entrance for receiving a stack of media items subsequent to presentation of the stack of media items to a customer.

Abstract: A process for fabricating a semiconductor device having deep trench structures includes forming a first portion of the trench in a semiconductor substrate and a second portion of the trench in a selectively-formed upper layer. After etching the substrate to form the first portion of the trench, a protective layer is deposited over the inner surface of the trench in the semiconductor substrate and the upper layer is selectively formed on a principal surface of the semiconductor substrate. During formation of the upper layer, a wall surface is formed in the upper layer that is continuous with the wall surface of the trench in the semiconductor substrate. By forming a second portion of the trench in the selectively-formed upper layer, a deep trench is produced having a high aspect ratio and well defined geometric characteristics.

Abstract: An edge protection process for semiconductor device fabrication includes forming a protective layer on the circumferential edge region of a semiconductor substrate. The semiconductor substrate is placed in a plasma atmosphere and trench structures, such as deep trenches and shallow trench isolation structures are etched in the substrate. The protective layer substantially prevents the etching of the circumferential edge region, such that the formation of black silicon is substantially minimized during the etching process.

Abstract: In a semiconductor manufacturing process for a dynamic random access memory, a buried insulator layer such as a buried SIMOX layer between trench capacitors isolates the capacitor from the access transistor, limiting leakage, improving device performance and simplifying manufacturing.