Patents by Inventor Michael Richard Ouellette
Michael Richard Ouellette has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8595557Abstract: A method for verifying the accuracy of memory testing software is disclosed. A built-in self test (BIST) fail control function is utilized to generate multiple simulated memory fails at various predetermined locations within a memory array of a memory device. The memory array is then tested by a memory tester. Afterwards, a bit fail map is generated by the logical-to-physical mapping software based on all the memory fails indicated by the memory tester. The bit fail map provides all the fail memory locations derived by the logical-to-physical mapping software. The fail memory locations derived by the logical-to-physical mapping software are then compared to the predetermined memory locations to verify the accuracy of the logical-to-physical mapping software.Type: GrantFiled: February 23, 2005Date of Patent: November 26, 2013Assignee: International Business Machines CorporationInventors: Eric Jasinski, Michael Richard Ouellette, Jeremy Paul Rowland
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Patent number: 8570820Abstract: The present invention relates to a method and circuit for selectively repairing an embedded memory module having memory elements in an integrated circuit chip. The method includes performing a plurality of tests on the embedded memory module under operating conditions to identify a plurality of non-operational memory elements in the embedded memory module and, in response to identifying the non-operational memory elements, generating a plurality of corresponding repair solutions. The method further includes storing the plurality of corresponding repair solutions in a non-volatile storage element and determining from a mask a subset of the plurality of repair solutions that should be restored.Type: GrantFiled: March 8, 2011Date of Patent: October 29, 2013Assignee: International Business Machines CorporationInventors: Kevin William Gorman, John Robert Goss, Michael Richard Ouellette, Troy Joseph Perry, Michael Anthony Ziegerhofer
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Publication number: 20120230136Abstract: The present invention relates to a method and circuit for selectively repairing an embedded memory module having memory elements in an integrated circuit chip. The method comprises performing a plurality of tests on the embedded memory module under operating conditions to identify a plurality of non-operational memory elements in the embedded memory module and, in response to identifying the non-operational memory elements, generating a plurality of corresponding repair solutions. The method further comprises storing the plurality of corresponding repair solutions in a non-volatile storage element and determining from a mask a subset of the plurality of repair solutions that should be restored.Type: ApplicationFiled: March 8, 2011Publication date: September 13, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin William Gorman, John Robert Goss, Michael Richard Ouellette, Troy Joseph Perry, Michael Anthony Ziegerhofer
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Patent number: 7930592Abstract: A design structure embodied in a machine readable medium for designing, manufacturing, testing and/or enabling a redundant memory element (20) during testing of a memory array (14), and a method of repairing a memory array.Type: GrantFiled: July 27, 2007Date of Patent: April 19, 2011Assignee: International Business Machines CorporationInventors: Michael Richard Ouellette, Jeremy Rowland
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Patent number: 7895028Abstract: A design structure which enables e-fuse memory repair. The design structure uses a compressed bit string to generate another bit string based on a select value. The select value provides instructions to an encoding logic element, which generates a second bit string. For example, the select value may instruct the encoding logic to create a duplicate copy of each bit in the compressed bit string to generate a 2n-bit string. Once the fuses are programmed using the second bit string, the fuse values are read out as a third string, which is decoded by a decoding logic element according to the select value, thereby improving memory repair.Type: GrantFiled: July 10, 2007Date of Patent: February 22, 2011Assignee: International Business Machines CorporationInventors: Darren Lane Anand, Michael Richard Ouellette, Michael Anthony Ziegerhofer
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Patent number: 7739637Abstract: Processing engines (PE's) disposed on the substrate. Each processing engine includes a measurement and storage unit, and a PE controller coupled to each of the processing engines. The processing engines perform self-tests and store the results of the self-tests in the measurement and storage unit. The PE controller reads the results and selects a sub-set of processing engines based on the results and an optimization algorithm.Type: GrantFiled: January 30, 2009Date of Patent: June 15, 2010Assignee: International Business Machines CorporationInventors: Kenneth Joseph Goodnow, Michael Richard Ouellette, Stephen Gerard Shuma, Peter Albert Twombly
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Patent number: 7735031Abstract: A system that includes a controller for enabling an enumeration operation. The enumeration operation is performed by a controller (110) and logic elements (120) in a system, such that each logic element in the system assigns itself a unique identifier. Each logic element can then be controlled by another source or have a means to communicate with other logic elements in the system. The unique identifier enables greater system flexibility, thereby reducing cost and improving efficiency.Type: GrantFiled: August 20, 2007Date of Patent: June 8, 2010Assignee: International Business Machines CorporationInventors: Valerie Hornbeck Chickanosky, Kevin William Gorman, Emory D. Keller, Michael Richard Ouellette
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Patent number: 7721119Abstract: A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.Type: GrantFiled: August 24, 2006Date of Patent: May 18, 2010Assignee: International Business Machines CorporationInventors: Louis Bennie Capps, Jr., Warren D. Dyckman, Joanne Ferris, Anand Haridass, James Douglas Jordan, Ronald Edward Newhart, Michael Richard Ouellette, Michael Jay Shapiro
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Patent number: 7688654Abstract: A design structure comprising a differential fuse sensing system, which includes a fuse leg configured for introducing a sense current through an electrically programmable fuse (eFUSE) to be sensed, and a differential sense amplifier having a first input node coupled to the fuse leg and a second node coupled to a reference voltage. The fuse leg further includes a current supply device controlled by a variable reference current generator configured to generate an output signal therefrom such that the voltage on the first input node of the sense amplifier is equal to the voltage on the second input node of the sense amplifier whenever the resistance value of the eFUSE is equal to the resistance value of a programmable variable resistance device included within the variable reference current generator.Type: GrantFiled: June 28, 2007Date of Patent: March 30, 2010Assignee: International Business Machines CorporationInventors: Darren Lane Anand, John Atkinson Fifield, Michael Richard Ouellette
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Publication number: 20090256591Abstract: Disclosed is a design structure for systems and methods of managing a set of programmable fuses on an integrated circuit.Type: ApplicationFiled: April 15, 2008Publication date: October 15, 2009Inventors: John Atkinson Fifield, Michael Richard Ouellette
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Patent number: 7541834Abstract: Disclosed is a design structure for systems and methods of managing a set of programmable fuses on an integrated circuit.Type: GrantFiled: May 15, 2008Date of Patent: June 2, 2009Assignee: International Business Machines CorporationInventors: John Atkinson Fifield, Michael Richard Ouellette
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Publication number: 20090052609Abstract: A system that includes a controller for enabling an enumeration operation. The enumeration operation is performed by a controller (110) and logic elements (120) in a system, such that each logic element in the system assigns itself a unique identifier. Each logic element can then be controlled by another source or have a means to communicate with other logic elements in the system. The unique identifier enables greater system flexibility, thereby reducing cost and improving efficiency.Type: ApplicationFiled: August 20, 2007Publication date: February 26, 2009Inventors: Valerie Hornbeck Chickanosky, Kevin William Gorman, Emory D. Keller, Michael Richard Ouellette
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Publication number: 20080052542Abstract: A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.Type: ApplicationFiled: August 24, 2006Publication date: February 28, 2008Inventors: Louis Bennie Capps, Warren D. Dyckman, Joanne Ferris, Anand Haridass, James Douglas Jordan, Ronald Edward Newhart, Michael Richard Ouellette, Michael Jay Shapiro
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Publication number: 20080001251Abstract: A design structure comprising a differential fuse sensing system, which includes a fuse leg configured for introducing a sense current through an electrically programmable fuse (eFUSE) to be sensed, and a differential sense amplifier having a first input node coupled to the fuse leg and a second node coupled to a reference voltage. The fuse leg further includes a current supply device controlled by a variable reference current generator configured to generate an output signal therefrom such that the voltage on the first input node of the sense amplifier is equal to the voltage on the second input node of the sense amplifier whenever the resistance value of the eFUSE is equal to the resistance value of a programmable variable resistance device included within the variable reference current generator.Type: ApplicationFiled: June 28, 2007Publication date: January 3, 2008Inventors: Darren Lane Anand, John Atkinson Fifield, Michael Richard Ouellette
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Patent number: 7251756Abstract: Integrated circuit memory is tested to discover defective memory elements. To replace the defective memory elements, spare memory elements are selected and a string is generated to indicate which ones of the spares replace which ones of the defective memory elements. The number of bits of the string depend upon how many of the memory elements are defective. Although a certain number of the memory elements are defective, which determines the number of the string bits, nevertheless, a number of fuses to program on the integrated circuit is determined responsive to how many fuses are available for programming relative to the number of the binary string bits. That is, if more fuses are available than a certain threshold number relative to the number of string bits (as is preferred), then more than the threshold number are programmed. If not, then only that certain threshold number of fuses are programmed.Type: GrantFiled: April 26, 2005Date of Patent: July 31, 2007Assignee: International Business Machines CorporationInventors: Darren Lane Anand, Michael Richard Ouellette, Michael Anthony Ziegerhofer
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Patent number: 7139944Abstract: A method and system for determining minimum post production test time on an integrated circuit device to achieve optimal reliability of that device utilizing defect counts. The number of defective cells or active elements with defective cells (DEFECTS) on the integrated circuit device are counted and this count serves as a basis for determining the minimum test time. A higher number of DEFECTS results in longer post production testing in order to achieve optimum reliability of the integrated circuit device. The number of DEFECTS can be counted on a device internal to the integrated circuit device and made available to determine the minimum required test time. The number of DEFECTS can also be obtained external to the integrated circuit device by intercepting information routed to another device. Information provided internally and externally can also reveal the physical location of DEFECTS to further refine the minimum required test time.Type: GrantFiled: August 25, 2003Date of Patent: November 21, 2006Assignee: International Business Machines CorporationInventors: Tange Nan Barbour, Thomas S. Barnett, Matthew Sean Grady, William Vincent Huott, Michael Richard Ouellette
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Patent number: 6577156Abstract: A method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox allows a reduction in the number of fuses required to repair or customize an integrated circuit and allows fuses to be grouped outside of the macros repaired by the fuses. The remote location of fuses allows flexibility in the placement of macros having redundant repair capability, as well as a preferable grouping of fuses for both programming convenience and circuit layout facilitation. The fuses are arranged in rows and columns and represent control words and run-length compressed data to provide a greater quantity of repair points per fuse. The data can be loaded serially into shift registers and shifted to the macro locations to control the selection of redundant circuits to repair integrated circuits having defects or to customize logic.Type: GrantFiled: December 5, 2000Date of Patent: June 10, 2003Assignee: International Business Machines CorporationInventors: Darren L. Anand, John Edward Barth, Jr., John Atkinson Fifield, Pamela Sue Gillis, Peter O. Jakobsen, Douglas Wayne Kemerer, David E. Lackey, Steven Frederick Oakland, Michael Richard Ouellette, William Robert Tonti
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Patent number: 6496432Abstract: A method and apparatus for testing a write function of a dual-port static memory cell during a concurrent read/write cycle on a memory cell is disclosed. A memory cell of a dual-port static memory is read via a first port of the memory cell. After the read operation, the standard bitline restore operation that normally occurs after a read or write operation is suppressed from occurring on the bitlines for the first port. Then, the memory cell is read again via the first port at the same time the memory cell is being written via a second port with a logical data value that is opposite to the logical data value being read from the first port. After the completion of the write operation, the bitlines for the first and second ports are restored by a bitline restore operation. Finally, the logical data value in the memory cell is verified for its correctness.Type: GrantFiled: December 8, 2000Date of Patent: December 17, 2002Assignee: International Business Machines CorporationInventors: Michael Richard Ouellette, Jeremy Paul Rowland, David Jerome Wager
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Patent number: 6442085Abstract: A testing method and device for detecting the existence of “stuck-open”, faults within static decoder circuits of a SRAM. The device and method make use of a novel pattern that fully tests static decoders used with an SRAM integrated circuit. The test pattern is selected so as to cause a transition on each parallel FET in a decoder circuit. The test pattern simulates multiple random accesses to the SRAM by modifying the traditional sequential, unique address pattern. The invention uses a two-dimensional pattern in that it separately tests rows and column decoders. In the first part of the test the input address to the column decoders is held constant while the row decoders are cycled through two sets of N iterations where N is the number of row address bits to be decoded. During the second part of the test the input address to the row decoders is held constant while the column decoders are cycled through two sets of M iterations where M is the number of column address bits to be decoded.Type: GrantFiled: October 2, 2000Date of Patent: August 27, 2002Assignee: International Business Machines CorporationInventors: Michael Thomas Fragano, Jeffery Howard Oppold, Michael Richard Ouellette, Jeremy Paul Rowland
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Publication number: 20020110024Abstract: A method and apparatus for testing a write function of a dual-port static memory cell during a concurrent read/write cycle on a memory cell is disclosed. A memory cell of a dual-port static memory is read via a first port of the memory cell. After the read operation, the standard bitline restore operation that normally occurs after a read or write operation is suppressed from occurring on the bitlines for the first port. Then, the memory cell is read again via the first port at the same time the memory cell is being written via a second port with a logical data value that is opposite to the logical data value being read from the first port. After the completion of the write operation, the bitlines for the first and second ports are restored by a bitline restore operation. Finally, the logical data value in the memory cell is verified for its correctness.Type: ApplicationFiled: December 8, 2000Publication date: August 15, 2002Applicant: International Business Machines CorporationInventors: Michael Richard Ouellette, Jeremy Paul Rowland, David Jerome Wager