Patents by Inventor Michael Riley Vinson
Michael Riley Vinson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230345642Abstract: The present invention relates to methods and systems for deposition of metal conductors using asymmetrical electrolytic plating, in which one surface (e.g., top) of a substrate is coated with an electrical conductor, and an opposite (e.g., bottom, or other) surface of which is not coated. A channel is formed between the two sides of the substrate, passing through the substrate and, in some embodiments, passing through the conductor. Electrolytic plating is performed such that metal is deposited from the edge of the conduct proximal to the channel, along the side walls of the channel, and up to, and in some embodiments on to, the other side of the substrate. Use of etching or plate resist layers are also contemplated.Type: ApplicationFiled: June 26, 2023Publication date: October 26, 2023Inventors: Michael Riley Vinson, Shinichi Iketani
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Patent number: 11716819Abstract: The present invention relates to methods and systems for deposition of metal conductors using asymmetrical electrolytic plating, in which one surface (e.g., top) of a substrate is coated with an electrical conductor, and an opposite (e.g., bottom, or other) surface of which is not coated. A channel is formed between the two sides of the substrate, passing through the substrate and, in some embodiments, passing through the conductor. Electrolytic plating is performed such that metal is deposited from the edge of the conduct proximal to the channel, along the side walls of the channel, and up to, and in some embodiments on to, the other side of the substrate. Use of etching or plate resist layers are also contemplated.Type: GrantFiled: June 21, 2019Date of Patent: August 1, 2023Assignee: Averatek CorporationInventors: Michael Riley Vinson, Shinichi Iketani
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Publication number: 20230201945Abstract: Compositions and methods for coupling metals to aluminum surfaces are provided. The compositions are prepared as aqueous solutions or suspensions, and can be applied to the aluminum surface using conventional printing techniques. Rheology of the printable composition can be adjusted to provide a gel or a cream. Curing steps, if necessary, are performed at low temperatures that are compatible with plastic/polymer components of mass produced devices, such as aluminum RFID antennae.Type: ApplicationFiled: March 7, 2023Publication date: June 29, 2023Inventors: Michael Riley VINSON, Calvin CHEN, Divyakant P. KADIWALA, Sunity K. SHARMA
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Patent number: 11597042Abstract: Compositions and methods for coupling metals to aluminum surfaces are provided. The compositions are prepared as aqueous solutions or suspensions, and can be applied to the aluminum surface using conventional printing techniques. Rheology of the printable composition can be adjusted to provide a gel or a cream. Curing steps, if necessary, are performed at low temperatures that are compatible with plastic/polymer components of mass produced devices, such as aluminum RFID antennae.Type: GrantFiled: November 20, 2018Date of Patent: March 7, 2023Assignee: Averatek CorporationInventors: Michael Riley Vinson, Calvin Chen, Divyakant P Kadiwala, Sunity K Sharma
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Publication number: 20220418113Abstract: Various inventions are disclosed in the microchip manufacturing arts. Conductive pattern formation by semi-additive processes are disclosed. Further conductive patterns and methods using activated precursors are also disclosed. Aluminum laminated surfaces and methods of circuit formation therefrom are further disclosed. Circuits formed on an aluminum heat sink are also disclosed. The inventive subject matter further discloses methods of electrolytic plating by controlling surface area of an anode.Type: ApplicationFiled: August 26, 2022Publication date: December 29, 2022Inventors: Michael Riley Vinson, Sunity K. Sharma, Haris Basit, Shinichi Iketani
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Publication number: 20210345498Abstract: Devices, methods, and systems for forming an electrical circuit out of a conductor embedded in two layers of substrate are disclosed. Portions of the two layers of substrate and the conductor are removed, forming a cavity through the two layers and the conductor. A blocker material is deposited along the wall of the cavity. A portion of the blocker material and adjacent layer of the substrate is removed forming another cavity in contact with a part of the conductor. A surface of the second cavity is then electroless plated by a conductive metal to form part of the electrical circuit.Type: ApplicationFiled: July 12, 2021Publication date: November 4, 2021Inventors: Shinichi IKETANI, Michael Riley VINSON, Haris BASIT
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Publication number: 20210265716Abstract: Systems, methods, and devices related to hollow metallic objects are disclosed. A solid sacrificial material is formed in a desired three-dimensional shape, and a precursor is deposited about an exterior surface of the solid sacrificial material. The precursor is used to deposit a first conductor about the exterior surface of the solid sacrificial material, and the solid sacrificial material is then removed. The first conductor assumes the three-dimensional shape, and is substantially hollow after removing the solid sacrificial material. Contemplated hollow metallic objects include waveguides, heat pipes, and vapor chambers.Type: ApplicationFiled: February 19, 2021Publication date: August 26, 2021Inventors: Haris BASIT, Michael Riley VINSON
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Publication number: 20210259112Abstract: Systems, methods, and devices related to catalyzed metal foils are disclosed. Contemplated metal foils have a bottom surface, preferably roughened to Ra of at least 0.1 ?m, bearing a catalyst material. The metal foils are etchable, typically of aluminum or derivative thereof, and is less than 500 ?m thick. Methods and systems for forming circuits from catalyzed metal foils are also disclosed. The catalyst material bearing surface of the metal foil is applied to a substrate and laminated, in some embodiments with a thermoset resin or thermoplastic resin therebetween or an organic material first coating the catalytic material. The metal foil is removed to expose the catalyst material, and a conductor is plated to the catalyst material.Type: ApplicationFiled: February 12, 2021Publication date: August 19, 2021Inventors: Shinichi IKETANI, Sunity K. SHARMA, Gary Lawrence BORGES, Michael Riley VINSON
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Patent number: 11076492Abstract: Devices, methods, and systems for forming an electrical circuit out of a conductor embedded in two layers of substrate are disclosed. Portions of the two layers of substrate and the conductor are removed, forming a cavity through the two layers and the conductor. A blocker material is deposited along the wall of the cavity. A portion of the blocker material and adjacent layer of the substrate is removed forming another cavity in contact with a part of the conductor. A surface of the second cavity is then electroless plated by a conductive metal to form part of the electrical circuit.Type: GrantFiled: December 17, 2019Date of Patent: July 27, 2021Assignee: Averatek CorporationInventors: Shinichi Iketani, Michael Riley Vinson, Haris Basit
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Publication number: 20210045252Abstract: Various inventions are disclosed in the microchip manufacturing arts. Conductive pattern formation by semi-additive processes are disclosed. Further conductive patterns and methods using activated precursors are also disclosed. Aluminum laminated surfaces and methods of circuit formation therefrom are further disclosed. Circuits formed on an aluminum heat sink are also disclosed. The inventive subject mater further discloses methods of electrolytic plating by controlling surface area of an anode.Type: ApplicationFiled: April 10, 2020Publication date: February 11, 2021Inventors: Haris BASIT, Michael Riley VINSON, Sunity K. SHARMA, Shinichi IKETANI, Divyakant KADIWALA
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Publication number: 20200232098Abstract: Methods of patterning electroless metals on a substrate are presented. The substrate is covered by a blocking reagent. After formation of a catalyst blocking layer on the substrate, portions of the catalyst blocking layer are removed to form a circuit pattern. A catalyst is placed the surfaces of both the catalyst blocking layer and the exposed substrate. The catalyst blocking layer prevents or reduces catalytic activity of the catalyst. Electroless metal plating is performed to plate a metal at the active portions of the catalyst.Type: ApplicationFiled: January 21, 2020Publication date: July 23, 2020Inventors: Michael Riley VINSON, Sunity K. SHARMA, Shinichi IKETANI, Calvin CHEN, Shalaka RAHANGDALE
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Publication number: 20200190670Abstract: Devices, systems, and methods are contemplated for depositing metals to the surface of a substrate. A first precursor ink including a metal is applied to a surface of the substrate, and the precursor ink is reduced to deposit the metal to the substrate, preferably by thermal reduction, forming a first metal layer. A second precursor ink having a second metal is then applied to the substrate, at least partially over the first metal layer. The second precursor ink is then reduced, typically by chemical reduction, depositing the second metal over the first metal layer in a globular fashion. Precursor inks are also disclosed having an alkyl metal carboxylate, a cyclic amine, and at least one of an ester, a hydrocarbon, or an ether.Type: ApplicationFiled: December 13, 2019Publication date: June 18, 2020Inventors: Sunity K SHARMA, Calvin CHEN, Shinichi IKETANI, Michael Riley VINSON
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Publication number: 20200196456Abstract: Devices, methods, and systems for forming an electrical circuit out of a conductor embedded in two layers of substrate are disclosed. Portions of the two layers of substrate and the conductor are removed, forming a cavity through the two layers and the conductor. A blocker material is deposited along the wall of the cavity. A portion of the blocker material and adjacent layer of the substrate is removed forming another cavity in contact with a part of the conductor. A surface of the second cavity is then electroless plated by a conductive metal to form part of the electrical circuit.Type: ApplicationFiled: December 17, 2019Publication date: June 18, 2020Inventors: Shinichi IKETANI, Michael Riley VINSON, Haris BASIT
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Publication number: 20200120811Abstract: Methods and systems are contemplated for making portions of electrical circuits with embedded electrical components, and the electrical circuits produced thereby. A layer of dielectric material is deposited over a substrate, and a cavity is formed in the dielectric material. An electrical component (e.g., integrated chip, etc.) is deposited in the cavity and covered by a further dielectric material, embedding the electrical component. Another cavity is formed in the further dielectric material, and a catalyst (e.g., electrolytic deposition catalyst, electroless deposition catalyst, etc.) is deposited over the further dielectric material and at least a portion of the electrical component. A conductor is then plated at the catalyst, preferably contacting the I/O ports of the electrical component.Type: ApplicationFiled: October 16, 2019Publication date: April 16, 2020Inventors: Haris BASIT, Michael Riley VINSON, Steve IKETANI
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Publication number: 20190394887Abstract: The present invention relates to methods and systems for deposition of metal conductors using asymmetrical electrolytic plating, in which one surface (e.g., top) of a substrate is coated with an electrical conductor, and an opposite (e.g., bottom, or other) surface of which is not coated. A channel is formed between the two sides of the substrate, passing through the substrate and, in some embodiments, passing through the conductor. Electrolytic plating is performed such that metal is deposited from the edge of the conduct proximal to the channel, along the side walls of the channel, and up to, and in some embodiments on to, the other side of the substrate. Use of etching or plate resist layers are also contemplated.Type: ApplicationFiled: June 21, 2019Publication date: December 26, 2019Inventors: Michael Riley Vinson, Shinichi Iketani
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Publication number: 20190394888Abstract: The present invention relates to methods and systems that utilize a catalyst or thin metal film by atomic level deposition (ALD) of one or more metals that allows fine traces deposition to the trench formed in a dielectric material, thereby minimizing potential physical damage due to embedded conductor format and making the fine space between traces to prevent electromigration in the traces.Type: ApplicationFiled: June 21, 2019Publication date: December 26, 2019Inventors: Shinichi Iketani, Michael Riley Vinson
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Publication number: 20190152002Abstract: Compositions and methods for coupling metals to aluminum surfaces are provided. The compositions are prepared as aqueous solutions or suspensions, and can be applied to the aluminum surface using conventional printing techniques. Rheology of the printable composition can be adjusted to provide a gel or a cream. Curing steps, if necessary, are performed at low temperatures that are compatible with plastic/polymer components of mass produced devices, such as aluminum RFID antennae.Type: ApplicationFiled: November 20, 2018Publication date: May 23, 2019Inventors: Michael Riley VINSON, Calvin CHEN, Divyakant P KADIWALA, Sunity K. SHARMA
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Publication number: 20180332713Abstract: Devices produced by patterning electroless metals on a substrate are presented. An active catalyst layer on the substrate is covered with a patterned mask and treated with a deactivating chemical reagent, which deactivates the catalyst layer not covered by the mask. Once the patterned mask is removed, the electroless metal layer can be placed to have a patterned electroless metals. Alternatively, a substrate can be coated with a blocking reagent in a pattern first to inhibit formation of the catalyst layer before a catalyst layer can be placed over the blocking agent layer and then electroless metal layer is placed on the catalyst layer. The pattern of the blocking reagent acts as a negative pattern of the final conductive line pattern.Type: ApplicationFiled: July 23, 2018Publication date: November 15, 2018Inventors: Mihir Reddy, Michael Riley Vinson, Sunity K. Sharma
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Patent number: 10034386Abstract: Methods and devices for patterning electroless metals on a substrate are presented. An active catalyst layer on the substrate can be covered with a patterned mask and treated with a deactivating chemical reagent, which deactivates the catalyst layer not covered by the mask. Once the patterned mask is removed, the electroless metal layer can be placed to have a patterned electroless metals. Alternatively, a substrate can be coated with a blocking reagent in a pattern first to inhibit formation of the catalyst layer before a catalyst layer can be placed over the blocking agent layer and then electroless metal layer is placed on the catalyst layer. The pattern of the blocking reagent acts as a negative pattern of the final conductive line pattern.Type: GrantFiled: June 23, 2017Date of Patent: July 24, 2018Assignee: AVERATEK CORPORATIONInventors: Mihir Reddy, Michael Riley Vinson, Sunity K. Sharma
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Publication number: 20170354040Abstract: Methods and devices for patterning electroless metals on a substrate are presented. An active catalyst layer on the substrate can be covered with a patterned mask and treated with a deactivating chemical reagent, which deactivates the catalyst layer not covered by the mask. Once the patterned mask is removed, the electroless metal layer can be placed to have a patterned electroless metals. Alternatively, a substrate can be coated with a blocking reagent in a pattern first to inhibit formation of the catalyst layer before a catalyst layer can be placed over the blocking agent layer and then electroless metal layer is placed on the catalyst layer. The pattern of the blocking reagent acts as a negative pattern of the final conductive line pattern.Type: ApplicationFiled: June 23, 2017Publication date: December 7, 2017Inventors: Mihir Reddy, Michael Riley Vinson, Sunity K. Sharma