Patents by Inventor Michael Robert May
Michael Robert May has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12218576Abstract: An isolated gate driver has a first portion in a first voltage domain and a second portion in a second voltage domain. The first and second portions are coupled by an isolation communication channel. The isolated gate driver transmits across the isolation communication channel a serial word containing first drive strength information and simultaneously transmits gate information with the serial word across the isolation communication channel. The gate information indicates a state of a gate signal for a transistor coupled to the second portion of the isolated gate driver. A demodulator circuit demodulates a signal containing the gate information and the drive strength information transmitted across the isolation communication channel in the serial word. A gate signal output circuit coupled to the demodulator circuit supplies the gate signal based on the gate information with a drive strength of the gate signal being based on the drive strength information.Type: GrantFiled: March 8, 2024Date of Patent: February 4, 2025Assignee: Skyworks Solutions, Inc.Inventors: Michael Robert May, Fernando Naim Lavalle Aviles, Carlos Jesus Briseno-Vidrios, Patrick De Bakker, Gabor Marek, Charles Guo Lin, Peter Onody, Tamas Marozsak, Andras V. Horvath
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Publication number: 20240348146Abstract: An isolated gate driver has a first portion in a first voltage domain and a second portion in a second voltage domain. The first and second portions are coupled by an isolation communication channel. The isolated gate driver transmits across the isolation communication channel a serial word containing first drive strength information and simultaneously transmits gate information with the serial word across the isolation communication channel. The gate information indicates a state of a gate signal for a transistor coupled to the second portion of the isolated gate driver. A demodulator circuit demodulates a signal containing the gate information and the drive strength information transmitted across the isolation communication channel in the serial word. A gate signal output circuit coupled to the demodulator circuit supplies the gate signal based on the gate information with a drive strength of the gate signal being based on the drive strength information.Type: ApplicationFiled: March 8, 2024Publication date: October 17, 2024Inventors: Michael Robert May, Fernando Naim Lavalle Aviles, Carlos Jesus Briseno-Vidrios, Patrick De Bakker, Gabor Marek, Charles Guo Lin, Peter Onody, Tamas Marozsak, Andras V. Horvath
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Patent number: 11962233Abstract: An isolated gate driver has a first portion in a first voltage domain and a second portion in a second voltage domain. The first and second portions are coupled by an isolation communication channel. The isolated gate driver transmits across the isolation communication channel a serial word containing first drive strength information and simultaneously transmits gate information with the serial word across the isolation communication channel. The gate information indicates a state of a gate signal for a transistor coupled to the second portion of the isolated gate driver. A demodulator circuit demodulates a signal containing the gate information and the drive strength information transmitted across the isolation communication channel in the serial word. A gate signal output circuit coupled to the demodulator circuit supplies the gate signal based on the gate information with a drive strength of the gate signal being based on the drive strength information.Type: GrantFiled: May 1, 2023Date of Patent: April 16, 2024Assignee: Skyworks Solutions, Inc.Inventors: Michael Robert May, Fernando Naim Lavalle Aviles, Carlos Jesus Briseno-Vidrios, Patrick Johannus De Bakker, Gabor Marek, Charles Guo Lin, Peter Onody, Tamas Marozsak, Andras V. Horvath
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Publication number: 20230387782Abstract: An isolated gate driver has a first portion in a first voltage domain and a second portion in a second voltage domain. The first and second portions are coupled by an isolation communication channel. The isolated gate driver transmits across the isolation communication channel a serial word containing first drive strength information and simultaneously transmits gate information with the serial word across the isolation communication channel. The gate information indicates a state of a gate signal for a transistor coupled to the second portion of the isolated gate driver. A demodulator circuit demodulates a signal containing the gate information and the drive strength information transmitted across the isolation communication channel in the serial word. A gate signal output circuit coupled to the demodulator circuit supplies the gate signal based on the gate information with a drive strength of the gate signal being based on the drive strength information.Type: ApplicationFiled: May 1, 2023Publication date: November 30, 2023Inventors: Michael Robert May, Fernando Naim Lavalle Aviles, Carlos Jesus Briseno-Vidrios, Patrick Johannus De Bakker, Gabor Marek, Charles Guo Lin, Peter Onody, Tamas Marozsak, Andras V. Horvath
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Publication number: 20230308090Abstract: A method for protecting a system including a driver integrated circuit includes receiving a driver input signal. The method includes driving an output signal externally to the driver integrated circuit. The output signal is driven based on the driver input signal and an indication of a delay between receipt of an edge of the driver input signal and arrival of a corresponding edge of the output signal at an output node coupled to a terminal of the driver integrated circuit.Type: ApplicationFiled: March 27, 2023Publication date: September 28, 2023Inventors: Peter Onody, Tamas Marozsak, Michael Robert May, Fernando Naim Lavalle Aviles, Patrick Johannus De Bakker
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Publication number: 20230208688Abstract: An integrated circuit includes a demodulator to demodulate a signal simultaneously transmitted over an isolation communication channel and obtain gate information and configuration information. The demodulator includes a gate demodulation path and a configuration demodulation path. The received signal oscillates at a first frequency to represent a first state, oscillates at different frequencies to represent a seconds state, oscillates at a third frequency (or third and fourth frequencies), which are lower than the first frequency, to represent a third state, and the received signal is steady state to represent a fourth state. The gate demodulation path detects the first and second states. The configuration demodulation path includes first and second sub-demodulation paths. An envelope detector in the first sub-demodulation path detects the second state and the second sub-demodulation path detects the third state. The configuration demodulation paths uses an output of the gate demodulation path.Type: ApplicationFiled: November 21, 2022Publication date: June 29, 2023Inventors: Carlos Jesus Briseno-Vidrios, Michael Robert May, Patrick Johannus De Bakker
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Publication number: 20230101417Abstract: An isolator product includes a capacitor having a first plate formed in a first conductive integrated circuit layer and multiple second plates formed in a second conductive integrated circuit layer. Each second plate of the multiple second plates is separated from a next adjacent second plate by a gap in the second conductive integrated circuit layer. The multiple second plates are concentric.Type: ApplicationFiled: September 29, 2022Publication date: March 30, 2023Inventors: Michael Robert May, Fernando Naim Lavalle Aviles
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Patent number: 9209912Abstract: Embodiments include circuit devices and methods for re-clocking an input signal. In an embodiment, a circuit device includes a data storage element having a data input to receive a digital data stream having a first clock rate and including a clock input to receive a clock signal having a second clock rate. The data storage element further includes logic to adjust edge timing of transitions within the digital data stream based on the clock signal to produce a modulated output signal having a power spectrum with spectral nulls at a desired frequency and its harmonics without changing an average data rate.Type: GrantFiled: November 18, 2009Date of Patent: December 8, 2015Assignee: Silicon Laboratories Inc.Inventors: Michael Robert May, Russell Croman, Younes Djadi, Scott Thomas Haban
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Patent number: 9041452Abstract: A circuit includes a power supply terminal and a clock parsing circuit configured to produce multiple clock signals having a common clock period and different phases. The circuit further includes a plurality of digital circuits coupled to the clock parsing circuit and the power supply terminal. Each digital circuit includes an input to receive data and logic to process the data. Each digital circuit is responsive to a phase associated with a respective clock signal of the multiple clock signals to draw current from the regulated power supply terminal to process the data to produce a data output. Additionally, the circuit includes an output timing management circuit coupled to each of the plurality of digital circuits and configured to control data outputs of each of plurality of digital circuits to prevent timing violations at one or more destination circuits.Type: GrantFiled: January 27, 2010Date of Patent: May 26, 2015Assignee: Silicon Laboratories Inc.Inventors: Michael Robert May, David S. Trager
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Patent number: 9036091Abstract: An integrated circuit includes a tuner, a digital television (DTV) demodulator, an analog television (ATV) demodulator, and a controller. The tuner includes an input for receiving a radio frequency (RF) signal including at least one of an analog television signal and digital television signal, and including a first output terminal and a second output terminal. The DTV demodulator includes a DTV input coupled to the first output terminal of the tuner and includes a DTV output terminal. The ATV demodulator includes an ATV input coupled to the second output terminal of the tuner and includes an ATV output terminal. The controller is coupled to the tuner, the DTV demodulator, and the ATV demodulator to configure the tuner and at least one of the DTV demodulator and the ATV demodulator for receiving television content in a selected television format.Type: GrantFiled: January 6, 2011Date of Patent: May 19, 2015Assignee: Silicon Laboratories Inc.Inventors: Alan F. Hendrickson, Alessandro Piovaccari, Ramin Khoini-Poorfard, Mitchell Reid, Frederick Alan Rush, Jean-Marc Guyot, David Le Goff, Michael Robert May, Henry William Singor, Qi Cai, Peter Jozef Vancorenland, Chunyu Xin, Pascal Blouin
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Patent number: 8564256Abstract: In an embodiment, a circuit includes a regulated power supply terminal, a processing circuit coupled to the regulated power supply terminal, and a low frequency responsive circuit having a first transistor adapted to be coupled to a power source and having first circuitry configured to control current flow from the power source through the first transistor to supply a low frequency current to the regulated power supply terminal. The circuit device further includes a high frequency responsive circuit having a second transistor coupled to the regulated power supply terminal and having second circuitry configured to control the second transistor to selectively modulate high frequency current components at the regulated power supply terminal to reduce voltage variations on the regulated power supply.Type: GrantFiled: November 18, 2009Date of Patent: October 22, 2013Assignee: Silicon Laboratories, Inc.Inventor: Michael Robert May
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Publication number: 20120176550Abstract: An integrated circuit includes a tuner, a digital television (DTV) demodulator, an analog television (ATV) demodulator, and a controller. The tuner includes an input for receiving a radio frequency (RF) signal including at least one of an analog television signal and digital television signal, and including a first output terminal and a second output terminal. The DTV demodulator includes a DTV input coupled to the first output terminal of the tuner and includes a DTV output terminal. The ATV demodulator includes an ATV input coupled to the second output terminal of the tuner and includes an ATV output terminal. The controller is coupled to the tuner, the DTV demodulator, and the ATV demodulator to configure the tuner and at least one of the DTV demodulator and the ATV demodulator for receiving television content in a selected television format.Type: ApplicationFiled: January 6, 2011Publication date: July 12, 2012Inventors: Alan F. Hendrickson, Alessandro Piovaccari, Ramin Khoini-Poorfard, Mitchell Reid, Frederick Alan Rush, Jean-Marc Guyot, David Le Goff, Michael Robert May, Henry William Singor, Qi Cai, Peter Jozef Vancorenland, Chunyu Xin, Pascal Blouin
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Publication number: 20110181325Abstract: A circuit includes a power supply terminal and a clock parsing circuit configured to produce multiple clock signals having a common clock period and different phases. The circuit further includes a plurality of digital circuits coupled to the clock parsing circuit and the power supply terminal. Each digital circuit includes an input to receive data and logic to process the data. Each digital circuit is responsive to a phase associated with a respective clock signal of the multiple clock signals to draw current from the regulated power supply terminal to process the data to produce a data output. Additionally, the circuit includes an output timing management circuit coupled to each of the plurality of digital circuits and configured to control data outputs of each of plurality of digital circuits to prevent timing violations at one or more destination circuits.Type: ApplicationFiled: January 27, 2010Publication date: July 28, 2011Applicant: SILICON LABORATORIES, INC.Inventors: Michael Robert May, David S. Trager
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Publication number: 20110158298Abstract: A tuner circuit includes a digital signal processor to generate a digital data stream related to a radio frequency signal and a transceiver circuit coupled to the digital signal processor and configurable to generate an inter-chip communication frame having a start portion and a plurality of channels. The plurality of channels includes a first data channel to carry a portion of the digital data stream and a control channel to carry control data. The transceiver circuit is configurable to send the inter-chip communication frame to an additional tuner circuit through an inter-chip communication link.Type: ApplicationFiled: December 30, 2009Publication date: June 30, 2011Applicant: SILICON LABORATORIES, INC.Inventors: Younes Djadi, Russell Croman, Scott Thomas Haban, Javier Elenes, Gerald Champagne, Michael Robert May
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Publication number: 20110115537Abstract: Embodiments include circuit devices and methods for re-clocking an input signal. In an embodiment, a circuit device includes a data storage element having a data input to receive a digital data stream having a first clock rate and including a clock input to receive a clock signal having a second clock rate. The data storage element further includes logic to adjust edge timing of transitions within the digital data stream based on the clock signal to produce a modulated output signal having a power spectrum with spectral nulls at a desired frequency and its harmonics without changing an average data rate.Type: ApplicationFiled: November 18, 2009Publication date: May 19, 2011Applicant: SILICON LABORATORIES, INC.Inventors: Michael Robert May, Russell Croman, Younes Djadi, Scott Thomas Haban
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Publication number: 20110115556Abstract: In an embodiment, a circuit includes a regulated power supply terminal, a processing circuit coupled to the regulated power supply terminal, and a low frequency responsive circuit having a first transistor adapted to be coupled to a power source and having first circuitry configured to control current flow from the power source through the first transistor to supply a low frequency current to the regulated power supply terminal. The circuit device further includes a high frequency responsive circuit having a second transistor coupled to the regulated power supply terminal and having second circuitry configured to control the second transistor to selectively modulate high frequency current components at the regulated power supply terminal to reduce voltage variations on the regulated power supply.Type: ApplicationFiled: November 18, 2009Publication date: May 19, 2011Applicant: SILICON LABORATORIES, INC.Inventor: Michael Robert May
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Patent number: 6081216Abstract: An oversampled analog-to-digital converter (ADC) (20) includes a sigma-delta modulator (21) with two decimation filters to provide minimum power consumption. The first decimation filter (30) converts the output of the sigma-delta modulator (21) to a slower intermediate frequency and performs a first part of the decimation function. The second decimation filter (40) converts the output of the first decimation filter (30) to the output frequency and performs a second part of the decimation function. The ADC (20) saves power by allowing some of the second part of the decimation function to be performed at the slower intermediate frequency. In one form, the first decimation filter (30) includes a finite impulse response (FIR) filter (32) and a down sampler (34). By using a suitable logic circuit (56), the FIR filter (32) can be implemented with only a small amount of circuit area and most of the FIR filter (32) can be operated at the slower intermediate frequency.Type: GrantFiled: June 11, 1998Date of Patent: June 27, 2000Assignee: Motorola, Inc.Inventor: Michael Robert May