Patents by Inventor Michael Roehner
Michael Roehner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10698022Abstract: In accordance with an embodiment of the present invention, a method of testing a plurality of semiconductor devices includes applying a stress voltage having a peak voltage on a shield line disposed over a substrate. The substrate has functional circuitry of a semiconductor device. A fixed voltage is applied to a first metal line disposed above the substrate adjacent the shield line. The first metal line is coupled to the functional circuitry and is configured to be coupled to a high voltage node during operation. The peak voltage is greater than a maximum fixed voltage. The shield line separates the first metal line from an adjacent second metal line configured to be coupled to a low voltage node during operation. The method further includes measuring a current through the shield line in response to the stress voltage, determining the current through the shield line of the semiconductor device, and based on the determination, identifying the semiconductor device as passing the test.Type: GrantFiled: April 11, 2018Date of Patent: June 30, 2020Assignee: Infineon Technologies AGInventors: Michael Roehner, Stefano Aresu
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Patent number: 10446534Abstract: In one embodiment, a capacitor includes a first row including a first capacitor element and a second capacitor element coupled in parallel, and a second row including a third capacitor element and a fourth capacitor element coupled in parallel. The first row is coupled in series with the second row. In a metallization level over a workpiece, the second capacitor element is disposed between the first capacitor element and the third capacitor element. In the metallization level, the third capacitor element is disposed between the second capacitor element and the fourth capacitor element. The first, the second, the third, and the fourth capacitor elements are disposed in the metallization level.Type: GrantFiled: October 15, 2016Date of Patent: October 15, 2019Assignee: Infineon Technologies AGInventors: Michael Roehner, Stefano Aresu
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Patent number: 10242922Abstract: A semiconductor wafer includes dielectric regions of different thicknesses, some of the dielectric regions being thinner and other ones of the dielectric regions being thicker. The semiconductor wafer further includes a stress circuit operable to stress at least one of the dielectric regions internally within the semiconductor wafer for assessing dielectric reliability. A corresponding method of internally assessing dielectric reliability of a semiconductor technology is also provided.Type: GrantFiled: January 9, 2014Date of Patent: March 26, 2019Assignee: Infineon Technologies AGInventors: Michael Röhner, Stefano Aresu, Marco Faricelli
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Publication number: 20180292450Abstract: In accordance with an embodiment of the present invention, a method of testing a plurality of semiconductor devices includes applying a stress voltage having a peak voltage on a shield line disposed over a substrate. The substrate has functional circuitry of a semiconductor device. A fixed voltage is applied to a first metal line disposed above the substrate adjacent the shield line. The first metal line is coupled to the functional circuitry and is configured to be coupled to a high voltage node during operation. The peak voltage is greater than a maximum fixed voltage. The shield line separates the first metal line from an adjacent second metal line configured to be coupled to a low voltage node during operation. The method further includes measuring a current through the shield line in response to the stress voltage, determining the current through the shield line of the semiconductor device, and based on the determination, identifying the semiconductor device as passing the test.Type: ApplicationFiled: April 11, 2018Publication date: October 11, 2018Inventors: Michael Roehner, Stefano Aresu
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Patent number: 9945899Abstract: In accordance with an embodiment of the present invention, a method of testing a plurality of semiconductor devices includes applying a stress voltage having a peak voltage on a shield line disposed over a substrate. The substrate has functional circuitry of a semiconductor device. A fixed voltage is applied to a first metal line disposed above the substrate adjacent the shield line. The first metal line is coupled to the functional circuitry and is configured to be coupled to a high voltage node during operation. The peak voltage is greater than a maximum fixed voltage. The shield line separates the first metal line from an adjacent second metal line configured to be coupled to a low voltage node during operation. The method further includes measuring a current through the shield line in response to the stress voltage, determining the current through the shield line of the semiconductor device, and based on the determination, identifying the semiconductor device as passing the test.Type: GrantFiled: May 24, 2016Date of Patent: April 17, 2018Assignee: Infineon Technologies AGInventors: Michael Roehner, Stefano Aresu
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Publication number: 20170033095Abstract: In one embodiment, a capacitor includes a first row including a first capacitor element and a second capacitor element coupled in parallel, and a second row including a third capacitor element and a fourth capacitor element coupled in parallel. The first row is coupled in series with the second row. In a metallization level over a workpiece, the second capacitor element is disposed between the first capacitor element and the third capacitor element. In the metallization level, the third capacitor element is disposed between the second capacitor element and the fourth capacitor element. The first, the second, the third, and the fourth capacitor elements are disposed in the metallization level.Type: ApplicationFiled: October 15, 2016Publication date: February 2, 2017Inventors: Michael Roehner, Stefano Aresu
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Patent number: 9508788Abstract: In one embodiment, a capacitor includes a first row including a first capacitor element and a second capacitor element coupled in parallel, and a second row including a third capacitor element and a fourth capacitor element coupled in parallel. The first row is coupled in series with the second row. In a metallization level over a workpiece, the second capacitor element is disposed between the first capacitor element and the third capacitor element. In the metallization level, the third capacitor element is disposed between the second capacitor element and the fourth capacitor element. The first, the second, the third, and the fourth capacitor elements are disposed in the metallization level.Type: GrantFiled: March 13, 2013Date of Patent: November 29, 2016Assignee: Infineon Technologies AGInventors: Michael Roehner, Stefano Aresu
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Publication number: 20160266197Abstract: In accordance with an embodiment of the present invention, a method of testing a plurality of semiconductor devices includes applying a stress voltage having a peak voltage on a shield line disposed over a substrate. The substrate has functional circuitry of a semiconductor device. A fixed voltage is applied to a first metal line disposed above the substrate adjacent the shield line. The first metal line is coupled to the functional circuitry and is configured to be coupled to a high voltage node during operation. The peak voltage is greater than a maximum fixed voltage. The shield line separates the first metal line from an adjacent second metal line configured to be coupled to a low voltage node during operation. The method further includes measuring a current through the shield line in response to the stress voltage, determining the current through the shield line of the semiconductor device, and based on the determination, identifying the semiconductor device as passing the test.Type: ApplicationFiled: May 24, 2016Publication date: September 15, 2016Inventors: Michael Roehner, Stefano Aresu
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Patent number: 9377502Abstract: In accordance with an embodiment of the present invention, a method of testing a plurality of semiconductor devices includes applying a stress voltage having a peak voltage on a shield line disposed over a substrate. The substrate has functional circuitry of a semiconductor device. A fixed voltage is applied to a first metal line disposed above the substrate adjacent the shield line. The first metal line is coupled to the functional circuitry and is configured to be coupled to a high voltage node during operation. The peak voltage is greater than a maximum fixed voltage. The shield line separates the first metal line from an adjacent second metal line configured to be coupled to a low voltage node during operation. The method further includes measuring a current through the shield line in response to the stress voltage, determining the current through the shield line of the semiconductor device, and based on the determination, identifying the semiconductor device as passing the test.Type: GrantFiled: December 19, 2013Date of Patent: June 28, 2016Assignee: Infineon Technologies AGInventors: Michael Roehner, Stefano Aresu
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Publication number: 20150194358Abstract: A semiconductor wafer includes dielectric regions of different thicknesses, some of the dielectric regions being thinner and other ones of the dielectric regions being thicker. The semiconductor wafer further includes a stress circuit operable to stress at least one of the dielectric regions internally within the semiconductor wafer for assessing dielectric reliability. A corresponding method of internally assessing dielectric reliability of a semiconductor technology is also provided.Type: ApplicationFiled: January 9, 2014Publication date: July 9, 2015Inventors: Michael Röhner, Stefano Aresu, Marco Faricelli
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Publication number: 20150177310Abstract: In accordance with an embodiment of the present invention, a method of testing a plurality of semiconductor devices includes applying a stress voltage having a peak voltage on a shield line disposed over a substrate. The substrate has functional circuitry of a semiconductor device. A fixed voltage is applied to a first metal line disposed above the substrate adjacent the shield line. The first metal line is coupled to the functional circuitry and is configured to be coupled to a high voltage node during operation. The peak voltage is greater than a maximum fixed voltage. The shield line separates the first metal line from an adjacent second metal line configured to be coupled to a low voltage node during operation. The method further includes measuring a current through the shield line in response to the stress voltage, determining the current through the shield line of the semiconductor device, and based on the determination, identifying the semiconductor device as passing the test.Type: ApplicationFiled: December 19, 2013Publication date: June 25, 2015Applicant: Infineon Technologies AGInventors: Michael Roehner, Stefano Aresu
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Publication number: 20150179534Abstract: In one embodiment of the present invention, a method of forming a semiconductor device includes performing a test during the forming of the semiconductor device within and/or over a substrate. A first voltage is applied to a first node coupled to a component to be tested in the substrate and a test voltage at a pad coupled to the component to be tested through a second node. The test voltage has a peak voltage higher than the first voltage. The component to be tested is coupled between the first node and the second node. A leakage current is measured through the component to be tested in response to the test voltage. After performing the test, the second node is connected to a functional block in the substrate. The first node is coupled to a third node coupled to the functional block.Type: ApplicationFiled: December 23, 2013Publication date: June 25, 2015Inventors: Michael Roehner, Stefano Aresu, Markus Zannoth
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Patent number: 9048150Abstract: In one embodiment of the present invention, a method of forming a semiconductor device includes performing a test during the forming of the semiconductor device within and/or over a substrate. A first voltage is applied to a first node coupled to a component to be tested in the substrate and a test voltage at a pad coupled to the component to be tested through a second node. The test voltage has a peak voltage higher than the first voltage. The component to be tested is coupled between the first node and the second node. A leakage current is measured through the component to be tested in response to the test voltage. After performing the test, the second node is connected to a functional block in the substrate. The first node is coupled to a third node coupled to the functional block.Type: GrantFiled: December 23, 2013Date of Patent: June 2, 2015Assignee: Infineon Technologies AGInventors: Michael Roehner, Stefano Aresu, Markus Zannoth
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Publication number: 20140273394Abstract: In one embodiment, a capacitor includes a first row including a first capacitor element and a second capacitor element coupled in parallel, and a second row including a third capacitor element and a fourth capacitor element coupled in parallel. The first row is coupled in series with the second row. In a metallization level over a workpiece, the second capacitor element is disposed between the first capacitor element and the third capacitor element. In the metallization level, the third capacitor element is disposed between the second capacitor element and the fourth capacitor element. The first, the second, the third, and the fourth capacitor elements are disposed in the metallization level.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Michael Roehner, Stefano Aresu
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Patent number: 6858492Abstract: Capacitor devices are formed in an essentially vertically extending fashion in order to achieve an essentially three-dimensional configuration or a configuration extending into the third dimension. A contacting of plug regions is performed after producing the capacitor devices. Such capacitor devices provide an increased integration density in a semiconductor memory device.Type: GrantFiled: July 1, 2002Date of Patent: February 22, 2005Assignee: Infineon Technologies AGInventors: Rainer Bruchhaus, Gerhard Enders, Walter Hartner, Matthias Krönke, Thomas Mikolajick, Nicolas Nagel, Michael Röhner
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Patent number: 6818503Abstract: A method of fabricating semiconductor memory devices is simplified by providing at least some plug regions, which are provided for contacting storage capacitor devices of a capacitor configuration, such that the plug regions have in each case a region that is elevated above the surface region of a passivation region.Type: GrantFiled: July 1, 2002Date of Patent: November 16, 2004Assignee: Infineon Technologies AGInventors: Rainer Bruchhaus, Gerhard Enders, Walter Hartner, Igor Kasko, Matthias Krönke, Thomas Mikolajick, Nicolas Nagel, Michael Röhner, Volker Weinrich
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Patent number: 6773986Abstract: To achieve a highest possible integration density in a semiconductor memory device having storage capacitors as storage elements, the method according to the invention forms the capacitor devices in substantially vertically extending fashion, to, as a result, achieve a substantially three-dimensional configuration and an configuration extending into the third dimension for the capacitor devices, a contact connection of the storage capacitors being formed after the production of the storage capacitors.Type: GrantFiled: July 1, 2002Date of Patent: August 10, 2004Assignee: Infineon Technologies AGInventors: Rainer Bruchhaus, Gerhard Enders, Walter Hartner, Matthias Krönke, Thomas Mikolajick, Nicolas Nagel, Michael Röhner
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Patent number: 6704219Abstract: To manufacture FeRAM memories in a particularly space-saving fashion and, thus, increase the storage density, a manufacturing method forms at least some of the multiplicity of capacitor devices used as storage elements with a multiplicity of individual capacitors that are connected in parallel with one another. The individual capacitors have ferroelectric or paraelectric dielectric regions with different coercitive voltages such that there is a resulting multiplicity of storage states for each of the individual capacitors.Type: GrantFiled: July 1, 2002Date of Patent: March 9, 2004Assignee: Infineon Technologies AGInventors: Rainer Bruchhaus, Gerhard Enders, Walter Hartner, Matthias Krönke, Thomas Mikolajick, Nicolas Nagel, Michael Röhner