Patents by Inventor Michael Roesner

Michael Roesner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180315713
    Abstract: An integrated circuit substrate and a method for manufacturing the same are disclosed. In an embodiment a method includes providing a wafer having a plurality of active areas, each active area being provided in a separate die area and for each active area, providing a code pattern outside the active area, the code pattern being associated with the die area.
    Type: Application
    Filed: July 9, 2018
    Publication date: November 1, 2018
    Inventors: Michael Roesner, Gudrun Stranzl, Manfred Engelhardt, Martin Zgaga
  • Patent number: 10032670
    Abstract: A method of forming a semiconductor device includes forming an active region in a first side of a silicon carbide substrate, the silicon carbide substrate having a second side opposite the first side and forming a contact pad at the first side. The contact pad is coupled to the active region. The method further includes forming an etch stop layer over the contact pad and plasma dicing the silicon carbide substrate from the second side. The plasma dicing etches through the silicon carbide substrate and stops on the etch stop layer. The diced silicon carbide substrate is held together by the etch stop layer. The diced silicon carbide substrate is attached on a carrier. The diced silicon carbide substrate is separated into silicon carbide dies by cleaving the etch stop layer.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: July 24, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Michael Roesner, Manfred Engelhardt, Gudrun Stranzl
  • Patent number: 10020264
    Abstract: The description discloses a method for use in manufacturing integrated circuit chips. The method comprises providing a wafer having a plurality of integrated circuits each provided in an separate active areas, and, for each active area, outside the active area, providing a code pattern that is associated with the integrated circuit. A computer-readable medium is also disclosed. Further, a manufacturing apparatus configured to receive a wafer and to remove material from the wafer so as to provide a scribe line to the wafer formed as a trench for use in separation of the wafer into dies is also disclosed. The description also discloses a wafer, an integrated circuit chip die substrate originating from a wafer of origin and carrying an integrated circuit, and an integrated circuit chip.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: July 10, 2018
    Assignee: Infineon Technologies AG
    Inventors: Michael Roesner, Gudrun Stranzl, Manfred Engelhardt, Martin Zgaga
  • Patent number: 10005659
    Abstract: A hole plate and a MEMS microphone arrangement are disclosed. In an embodiment a hole plate includes a substrate with a first main surface, a second main surface, and a lateral surface and a perforation structure formed within the substrate, the perforation structure having a plurality of through-holes through the substrate, wherein the through-holes and the lateral surface are a result of a simultaneous dry etching step.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: June 26, 2018
    Assignee: Infineon Technologies AG
    Inventors: Thomas Grille, Ursula Hedenig, Michael Roesner, Gudrun Stranzl, Martin Zgaga
  • Patent number: 9911686
    Abstract: A method for forming a semiconductor device includes forming device regions in a semiconductor substrate having a first side and a second side. The device regions are formed adjacent the first side. The method further includes forming a seed layer over the first side of the semiconductor substrate, and forming a patterned resist layer over the seed layer. A contact pad is formed over the seed layer within the patterned resist layer. The method further includes removing the patterned resist layer after forming the contact pad to expose a portion of the seed layer underlying the patterned resist layer, and forming a protective layer over the exposed portion of the seed layer.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: March 6, 2018
    Assignee: Infineon Technologies AG
    Inventors: Manfred Schneegans, Andreas Meiser, Martin Mischitz, Michael Roesner, Michael Pinczolits
  • Publication number: 20180005838
    Abstract: A segmented edge protection shield for plasma dicing a wafer. The segmented edge protection shield includes an outer structure and a plurality of plasma shield edge segments. The outer structure defines an interior annular edge configured to correspond to the circumferential edge of the wafer. Each one of the plurality of plasma shield edge segments is defined by an inner edge and side edges. The inner edge is interior to and concentric to the annular edge of the outer structure. The side edges extend between the inner edge and the annular edge.
    Type: Application
    Filed: September 18, 2017
    Publication date: January 4, 2018
    Applicant: Infineon Technologies AG
    Inventors: Manfred Engelhardt, Michael Roesner, Georg Ehrentraut
  • Publication number: 20170358494
    Abstract: A method of forming a semiconductor device includes forming an active region in a first side of a silicon carbide substrate, the silicon carbide substrate having a second side opposite the first side and forming a contact pad at the first side. The contact pad is coupled to the active region. The method further includes forming an etch stop layer over the contact pad and plasma dicing the silicon carbide substrate from the second side. The plasma dicing etches through the silicon carbide substrate and stops on the etch stop layer. The diced silicon carbide substrate is held together by the etch stop layer. The diced silicon carbide substrate is attached on a carrier. The diced silicon carbide substrate is separated into silicon carbide dies by cleaving the etch stop layer.
    Type: Application
    Filed: June 14, 2016
    Publication date: December 14, 2017
    Inventors: Michael Roesner, Manfred Engelhardt, Gudrun Stranzl
  • Patent number: 9793129
    Abstract: A segmented edge protection shield for plasma dicing a wafer. The segmented edge protection shield includes an outer structure and a plurality of plasma shield edge segments. The outer structure defines an interior annular edge configured to correspond to the circumferential edge of the wafer. Each one of the plurality of plasma shield edge segments is defined by an inner edge and side edges. The inner edge is interior to and concentric to the annular edge of the outer structure. The side edges extend between the inner edge and the annular edge.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: October 17, 2017
    Assignee: Infineon Technologies AG
    Inventors: Manfred Engelhardt, Michael Roesner, Georg Ehrentraut
  • Publication number: 20170207123
    Abstract: According to various embodiments, a method for processing a substrate may include: processing a plurality of device regions in a substrate separated from each other by dicing regions, each device region including at least one electronic component; wherein processing each device region of the plurality of device regions includes: forming a recess into the substrate in the device region, wherein the recess is defined by recess sidewalls of the substrate, wherein the recess sidewalls are arranged in the device region; forming a contact pad in the recess to electrically connect the at least one electronic component, wherein the contact pad has a greater porosity than the recess sidewalls; and singulating the plurality of device regions from each other by dicing the substrate in the dicing region.
    Type: Application
    Filed: January 18, 2016
    Publication date: July 20, 2017
    Inventors: Martin MISCHITZ, Markus HEINRICI, Michael ROESNER, Oliver HELLMUND, Caterina TRAVAN, Manfred SCHNEEGANS, Peter IRSIGLER, Friedrich KROENER
  • Patent number: 9704748
    Abstract: A method of dicing a wafer includes providing a wafer and etching the wafer to singulate die between kerf line segments defined within an interior region of the wafer and to singulate a plurality of wafer edge areas between the kerf line segments and a circumferential edge of the wafer. Each one of the plurality of wafer edge areas is singulated by kerf lines that each extend between one of two endpoints of one of the kerf line segments and the circumferential edge of the wafer.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: July 11, 2017
    Assignee: Infineon Technologies AG
    Inventors: Joerg Ortner, Michael Roesner, Gudrun Stranzl, Rudolf Rothmaler
  • Publication number: 20170158493
    Abstract: A hole plate and a MEMS microphone arrangement are disclosed. In an embodiment a hole plate includes a substrate with a first main surface, a second main surface, and a lateral surface and a perforation structure formed within the substrate, the perforation structure having a plurality of through-holes through the substrate, wherein the through-holes and the lateral surface are a result of a simultaneous dry etching step.
    Type: Application
    Filed: February 23, 2017
    Publication date: June 8, 2017
    Inventors: Thomas Grille, Ursula Hedenig, Michael Roesner, Gudrun Stranzl, Martin Zgaga
  • Patent number: 9673096
    Abstract: According to various embodiments, a method for processing a semiconductor substrate may include: covering a plurality of die regions of the semiconductor substrate with a metal; forming a plurality of dies from the semiconductor substrate, wherein each die of the plurality of dies is covered with the metal; and, subsequently, annealing the metal covering at least one die of the plurality of dies.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: June 6, 2017
    Assignees: INFINEON TECHNOLOGIES AG, Technische Universitaet Graz
    Inventors: Joachim Hirschler, Michael Roesner, Markus Juch Heinrici, Gudrun Stranzl, Martin Mischitz, Martin Zgaga
  • Patent number: 9640419
    Abstract: In accordance with an alternative embodiment of the present invention, a method for forming a semiconductor device includes applying a paste over a semiconductor substrate, and forming a ceramic carrier by solidifying the paste. The semiconductor substrate is thinned using the ceramic carrier as a carrier.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: May 2, 2017
    Assignee: Infineon Technologies AG
    Inventors: Manfred Schneegans, Martin Mischitz, Michael Roesner, Michael Pinczolits
  • Patent number: 9610543
    Abstract: A method for structuring a substrate and a structured substrate are disclosed. In an embodiment a method includes providing a substrate with a first main surface and a second main surface, wherein the substrate is fixed to a carrier arrangement at the second main surface, performing a photolithography step at the first main surface of the substrate to mark a plurality of sites at the first main surface, the plurality of sites corresponding to future perforation structures and future kerf regions for a plurality of future individual semiconductor chips to be obtained from the substrate, and plasma etching the substrate at the plurality of sites until the carrier arrangement is reached, thus creating the perforation structures within the plurality of individual semiconductor chips and simultaneously separating the individual semiconductor chips along the kerf regions.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: April 4, 2017
    Assignee: Infineon Technologies AG
    Inventors: Thomas Grille, Ursula Hedenig, Michael Roesner, Gudrun Stranzl, Martin Zgaga
  • Publication number: 20170076970
    Abstract: Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece.
    Type: Application
    Filed: November 23, 2016
    Publication date: March 16, 2017
    Inventors: Gudrun Stranzl, Martin Zgaga, Rainer Leuschner, Bernhard Goller, Bernhard Boche, Manfred Engelhardt, Hermann Wendt, Bernd Noehammer, Karl Mayer, Michael Roesner, Monika Cornelia Voerckel
  • Publication number: 20160379884
    Abstract: A method of dicing a wafer includes providing a wafer and etching the wafer to singulate die between kerf line segments defined within an interior region of the wafer and to singulate a plurality of wafer edge areas between the kerf line segments and a circumferential edge of the wafer. Each one of the plurality of wafer edge areas is singulated by kerf lines that each extend between one of two endpoints of one of the kerf line segments and the circumferential edge of the wafer.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 29, 2016
    Inventors: Joerg Ortner, Michael Roesner, Gudrun Stranzl, Rudolf Rothmaler
  • Publication number: 20160343574
    Abstract: A segmented edge protection shield for plasma dicing a wafer. The segmented edge protection shield includes an outer structure and a plurality of plasma shield edge segments. The outer structure defines an interior annular edge configured to correspond to the circumferential edge of the wafer. Each one of the plurality of plasma shield edge segments is defined by an inner edge and side edges. The inner edge is interior to and concentric to the annular edge of the outer structure. The side edges extend between the inner edge and the annular edge.
    Type: Application
    Filed: May 20, 2015
    Publication date: November 24, 2016
    Inventors: Manfred Engelhardt, Michael Roesner, Georg Ehrentraut
  • Patent number: 9496193
    Abstract: A semiconductor chip includes a body having a frontside, a backside opposite the frontside, and sidewalls extending between the backside and frontside, at least a portion of each sidewall having a defined surface structure with hydrophobic characteristics to inhibit travel of a bonding material along the sidewalls during attachment of the semiconductor chip to a carrier with the bonding material.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: November 15, 2016
    Assignee: Infineon Technologies AG
    Inventors: Michael Roesner, Gudrun Stranzl, Martin Zgaga, Martin Sporn, Tobias Schmidt
  • Publication number: 20160322306
    Abstract: The description discloses a method for use in manufacturing integrated circuit chips. The method comprises providing a wafer having a plurality of integrated circuits each provided in an separate active areas, and, for each active area, outside the active area, providing a code pattern that is associated with the integrated circuit. A computer-readable medium is also disclosed. Further, a manufacturing apparatus configured to receive a wafer and to remove material from the wafer so as to provide a scribe line to the wafer formed as a trench for use in separation of the wafer into dies is also disclosed. The description also discloses a wafer, an integrated circuit chip die substrate originating from a wafer of origin and carrying an integrated circuit, and an integrated circuit chip.
    Type: Application
    Filed: April 28, 2015
    Publication date: November 3, 2016
    Inventors: Michael Roesner, Gudrun Stranzl, Manfred Engelhardt, Martin Zgaga
  • Patent number: 9455192
    Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes attaching a substrate to a carrier using an adhesive component and forming a through trench through the substrate to expose the adhesive component. At least a portion of the adhesive component is etched and a metal layer is formed over sidewalls of the through trench.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: September 27, 2016
    Assignee: Infineon Technologies AG
    Inventors: Michael Roesner, Manfred Engelhardt, Johann Schmid, Gudrun Stranzl, Joachim Hirschler