Abstract: In some embodiments, a PPM interface for a computing platform may be provided with functionality to facilitate, to an OS through the PPM interface, firmware performance data.

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine if a wake event corresponds to a zero-power state of a computer operating system, determine if a run-time state is valid to wake the operating system from the zero-power state, and wake the operating system from the zero-power state to the run-time state if the run-time state is determined to be valid. Other embodiments are disclosed and claimed.

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine respective priority levels for one or more boot time events, determine an amount of execution time for the one or more boot time events, and automatically adjust a timer based on the amount of execution time and the priority levels for the one or more boot time events. Other embodiments are disclosed and claimed.

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine one or more filtered memory locations of a memory, determine if a read access for the memory corresponds to the one or more filtered memory locations, and return a pre-determined filter value as a result of the read access if the read access is determined to correspond to the one or more filtered memory locations. Other embodiments are disclosed and claimed.

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine if a wake event corresponds to a zero-power state of a computer operating system, determine if a run-time state is valid to wake the operating system from the zero-power state, and wake the operating system from the zero-power state to the run-time state if the run-time state is determined to be valid. Other embodiments are disclosed and claimed.

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine respective priority levels for one or more boot time events, determine an amount of execution time for the one or more boot time events, and automatically adjust a timer based on the amount of execution time and the priority levels for the one or more boot time events. Other embodiments are disclosed and claimed.

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine one or more filtered memory locations of a memory, determine if a read access for the memory corresponds to the one or more filtered memory locations, and return a pre-determined filter value as a result of the read access if the read access is determined to correspond to the one or more filtered memory locations. Other embodiments are disclosed and claimed.

Abstract: In some embodiments, a PPM interface for a computing platform may be provided with functionality to facilitate, to an OS through the PPM interface, firmware performance data.

Abstract: A non-volatile random access memory (NVRAM) is used in a computer system to provide instant responses to sleep state transitions. The computer system includes a processor coupled to an NVRAM, which is accessible by the processor without passing through an I/O subsystem. The NVRAM is byte-rewritable and byte-erasable by the processor. In response to a request to enter a powered sleep state, the computer system converts the powered sleep state into a powered-off sleep state with system memory context stored in the NVRAM. The powered sleep state is defined as a state in which power is supplied to volatile random access memory in the computer system, and the powered-off sleep state is defined as a state in which power is removed from the volatile random access memory. In response to a wake event, the computer system resumes working state operations using the system memory context stored in the NVRAM.

Abstract: In some embodiments, a PPM interface for a computing platform may be provided with functionality to facilitate, to an OS through the PPM interface, firmware performance data.

Abstract: In some embodiments, a PPM interface for a computing platform may be provided with functionality to facilitate, to an OS through the PPM interface, firmware performance data.

Abstract: In some embodiments, a PPM interface for a computing platform may be provided with functionality to facilitate, to an OS through the PPM interface, firmware performance data.

Abstract: Multiple operational contexts are called up from a Standby power state of a computing device. The operational contexts run on one or more operating systems of the computing device. When a desired operational context is chosen, such as by activation through a user initiated act or hot key, the operating system supporting the desired operational context is booted up from the Standby power state.

Abstract: A consumer financial transaction system is provided by a lending institution enabling a consumer to make transactions via a transaction device. The system includes a database storage device for maintaining a plurality of databases configured to store information corresponding to both credit and deposit accounts held by each of the consumers with the lending institution. A server maintains a secondary transaction module configured to apportion a withdrawal for a transaction among a consumer's credit account and any other one of the consumer's credit accounts and any of the consumer's deposit accounts maintained by the consumer with the lending institution.

Abstract: The subject matter herein relates to data processing and, more particularly, to encryption acceleration. Various embodiments herein provide devices and systems including a standardized encryption application programming interface embedded in firmware to perform encryption services. Some such embodiments move encryption operations away from operating system processes into firmware. As a result, encryption operations are generally accelerated.

Abstract: A consumer financial transaction system enables a consumer to make transactions via a transaction device. The system has a database storage device for maintaining several databases which are configured to store information corresponding to accounts held by each of the consumers. The server maintains a compute interest pledge module configured to calculate a credit interest rate corresponding to one or more deposit accounts maintained by the consumer, at least of portion of which is pledged by the consumer as a security against the consumer's credit account. In another embodiment, a secondary transaction module is configured to store preferences for apportioning a withdrawal for a transaction between a consumer's credit account and a consumer's deposit accounts.

Abstract: In some embodiments, a PPM interface for a computing platform may he provided with functionality to facilitate, to an OS through the PPM interface, firmware performance data.

Abstract: When transitioning from sleep mode to active mode, a processing system loads first stage resume content and second stage resume content into a volatile memory of the processing system. The first stage resume content may contain contextual data for a first program that was in use before the processing system transitioned to sleep mode. The second stage resume content may contain contextual data for another program that was in use before the processing system transitioned to sleep mode. The processing system may provide a user interface for the first program before all of the second stage resume content has been loaded into the volatile memory. Other embodiments are described and claimed.

Abstract: A non-volatile random access memory (NVRAM) is used in a computer system to provide instant responses to sleep state transitions. The computer system includes a processor coupled to an NVRAM, which is accessible by the processor without passing through an I/O subsystem. The NVRAM is byte-rewritable and byte-erasable by the processor. In response to a request to enter a powered sleep state, the computer system converts the powered sleep state into a powered-off sleep state with system memory context stored in the NVRAM. The powered sleep state is defined as a state in which power is supplied to volatile random access memory in the computer system, and the powered-off sleep state is defined as a state in which power is removed from the volatile random access memory. In response to a wake event, the computer system resumes working state operations using the system memory context stored in the NVRAM.

Abstract: When transitioning from sleep mode to active mode, a processing system loads first stage resume content and second stage resume content into a volatile memory of the processing system. The first stage resume content may contain contextual data for a first program that was in use before the processing system transitioned to sleep mode. The second stage resume content may contain contextual data for another program that was in use before the processing system transitioned to sleep mode. The processing system may provide a user interface for the first program before all of the second stage resume content has been loaded into the volatile memory. Other embodiments are described and claimed.