Abstract: A testing device for testing a distance sensor includes a receiving element for receiving an electromagnetic free-space wave as a receive signal, and a radiating element for radiating a simulated reflection signal. The receive signal or a signal derived therefrom is routed via a time delay circuit, and is thus time-delayed to a time-delayed signal. The time-delayed signal or a signal derived therefrom is radiated as the simulated reflection signal. The time delay circuit has an analog delay path and a digital delay path. The analog delay path implements shorter time delays than the digital delay path, apart from a possible overlap region. An input switch is used to switch the receive signal or the signal derived therefrom to the input of the analog delay path or to the input of the digital delay path, and the signal becomes the time-delayed signal after passing through the connected delay path.

Abstract: A test bench (1) is described and shown for testing a distance sensor (2) operating with electromagnetic waves, wherein the distance sensor (2) to be tested comprises at least one sensor radiating element (3a) for radiating a transmission signal (4) and a sensor receiving element (3b) for receiving a reflection signal, with a receptacle (5) for holding the distance sensor (2) to be tested, with an at least partially movable connecting member (6, 6m, 6s) in the radiation area of a distance sensor (2) held in the receptacle (5), with at least one test bench receiving element (7) held in the connecting member (6, 6m, 6s) for receiving a transmission signal (4) radiated by the sensor radiating element (3a), and with at least one test bench radiating element (8) held in the connecting member (6) for radiating a test bench transmitting signal (9) as a simulated reflection signal.

Abstract: A testing device for testing a distance sensor includes a receiving element for receiving an electromagnetic free-space wave as a receive signal, and a radiating element for radiating a simulated reflection signal. The receive signal or a signal derived therefrom is routed via a time delay circuit, and is thus time-delayed to a time-delayed signal. The time-delayed signal or a signal derived therefrom is radiated as the simulated reflection signal. The time delay circuit has an analog delay path and a digital delay path. The analog delay path implements shorter time delays than the digital delay path, apart from a possible overlap region. An input switch is used to switch the receive signal or the signal derived therefrom to the input of the analog delay path or to the input of the digital delay path, and the signal becomes the time-delayed signal after passing through the connected delay path.

Abstract: A test bench (1) is described and shown for testing a distance sensor (2) operating with electromagnetic waves, wherein the distance sensor (2) to be tested comprises at least one sensor radiating element (3a) for radiating a transmission signal (4) and a sensor receiving element (3b) for receiving a reflection signal, with a receptacle (5) for holding the distance sensor (2) to be tested, with an at least partially movable connecting member (6, 6m, 6s) in the radiation area of a distance sensor (2) held in the receptacle (5), with at least one test bench receiving element (7) held in the connecting member (6, 6m, 6s) for receiving a transmission signal (4) radiated by the sensor radiating element (3a), and with at least one test bench radiating element (8) held in the connecting member (6) for radiating a test bench transmitting signal (9) as a simulated reflection signal.

Abstract: A test bench for testing a distance radar instrument for determining distance and speed of obstacles, comprising a radar emulation device comprising at least one radar antenna and a computer unit with a model of the surroundings, wherein the model of the surroundings comprises data (x, v) of at least one obstacle with a relative position and speed from the distance radar instrument, wherein the radar emulation device emits a suitable reflection radar signal on the basis of the relative position and speed predetermined by the model of the surroundings at least partly in the direction of the distance radar instrument after receiving a scanning radar signal from the distance radar instrument such that the distance radar instrument detects an obstacle with a predetermined relative position and speed, wherein the radar emulation device extends over an angular range in front of the distance radar instrument such that the obstacle with relative position and speed can be simulated in this angular range with mutually

Abstract: A test bench for testing a distance radar instrument for determining distance and speed of obstacles, comprising a radar emulation device comprising at least one radar antenna and a computer unit with a model of the surroundings, wherein the model of the surroundings comprises data (x, v) of at least one obstacle with a relative position and speed from the distance radar instrument, wherein the radar emulation device emits a suitable reflection radar signal on the basis of the relative position and speed predetermined by the model of the surroundings at least partly in the direction of the distance radar instrument after receiving a scanning radar signal from the distance radar instrument such that the distance radar instrument detects an obstacle with a predetermined relative position and speed, wherein the radar emulation device extends over an angular range in front of the distance radar instrument such that the obstacle with relative position and speed can be simulated in this angular range with mutually

Abstract: The data and clock regeneration circuit can be completely integrated in a chip. The circuit has, in series, two independent PLL regulating stages which are optimally adjustable separately. The first PLL regulating stage has a large bandwidth and is optimized for maximum jitter tolerance and the second PLL regulating stage has a small bandwidth and is optimized for minimum jitter transfer. The circuit is suitable for use, for example, in transceivers for ATM, SONET, and SDH applications with signal transmission links in the Gbit range.

Abstract: The data and clock regeneration circuit can be completely integrated in a chip. The circuit has, in series, two independent PLL regulating stages which are optimally adjustable separately. The first PLL regulating stage has a large bandwidth and is optimized for maximum jitter tolerance and the second PLL regulating stage has a small bandwidth and is optimized for minimum jitter transfer. The circuit is suitable for use, for example, in transceivers for ATM, SONET, and SDH applications with signal transmission links in the Gbit range.