Abstract: A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes an integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit connected with an electronic data source for receiving reads of genomic data. The hardwired digital logic circuits are arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired digital logic circuits to perform one or more steps in the sequence analysis pipeline on the reads of genomic data. Each subset of the hardwired digital logic circuits is formed in a wired configuration to perform the one or more steps in the sequence analysis pipeline.

Abstract: A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes an integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit connected with an electronic data source for receiving reads of genomic data. The hardwired digital logic circuits are arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired digital logic circuits to perform one or more steps in the sequence analysis pipeline on the reads of genomic data. Each subset of the hardwired digital logic circuits is formed in a wired configuration to perform the one or more steps in the sequence analysis pipeline.

Abstract: In a DFA, a sub-scan is executed during a DFA scan. The sub-scan consumes input symbols out of sequence relative to the DFA scan, either forward or in reverse. An input symbol in the DFA scan is matched. A sub-scan command is supplied to the DFA. The sub-scan command is executed and at least one symbol is consumed in the sub-scan.

Abstract: Cost factors are utilized and may be estimated to determine split points in a DFA-NFA hybrid. The cost factors may comprise NFA start states, DFA backup factor, DFA-NFA token frequency, DFA steps to match, and NFA states to match. Other cost factors may be used as necessary. The cost factors are multiplied by tunable coefficients and summed. NFA states at minimum cost points are determined for entrance states in the NFA. A DFA is compiled from the entrance paths to the entrance states. NFA states and transitions needed only to reach entrance states may be deleted and all remaining NFA states are made available for execution by the NFA engine. An NFA representation of an NFA is examined by bounded depth-first recursion from each start state.

Abstract: A composite DFA for multiple regular expressions or other rules may be generated in a two-step process—first compiling single rule DFAs, then performing subset construction on those DFAs to generate the composite DFA, with subset information retained. A new batch of one or more rules may be added by another subset construction from the old composite DFA and new single rule DFAs, with subset information for the new composite DFA compressed into sets of states from old and new single rule DFAs. A batch of one or more rules is deleted by deleting references to single rule DFA states from composite DFA subsets, deleting composite DFA states with empty subsets and merging composite DFA states with identical subsets. Rules are changed by deleting the old versions and then adding the new versions.

Abstract: A character class (CCL) memory containing simple CCLs represented by encoding contained symbols or minimum and maximum symbols of a range, complex CCLs represented by bit-masks indicating contained symbols, and equivalence class (EC) maps represented as tables of ED values for each symbol value. Determining a next DFA transition by comparing multiple CCLs with a single input symbol, and selecting a transition according to the first matching CCL, or selecting a transition corresponding to a vector of CCL match result bits. Comparing CCLs from one DFA instruction to determine a transition and if no CCLs match, comparing CCLs from a second DDFA instruction to determine the transition. Matching linear sequence of two or more DFA states using a sequence of multiple CCLs encoded in a single DFA instruction.

Abstract: A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes an integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit connected with an electronic data source for receiving reads of genomic data. The hardwired digital logic circuits are arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired digital logic circuits to perform one or more steps in the sequence analysis pipeline on the reads of genomic data. Each subset of the hardwired digital logic circuits is formed in a wired configuration to perform the one or more steps in the sequence analysis pipeline.

Abstract: In a DFA scanning engine used to match regular expressions or similar rules, instructions to execute DFA state transitions are accessed through an instruction cache. Each DFA instruction may indicate varying numbers of transitions or branches from a current state. The cache pre-fetches a requested number of additional instructions consecutively following an accessed instruction. The DFA engine accesses an instruction from the cache corresponding to a state within a small number of transitions from the root state. When a low-branching instruction is executed to access a next instruction from the root state, or when a low-branching instruction is executed to access a next instruction from the cache, a fixed or configurable pre-fetch length is requested. Some instructions such as low-branching instructions may contain a pre-fetch hint.

Abstract: Disclosed is a hardware NFA cell array used to find matches to regular expressions or other rules in an input symbol stream scans multiple symbols per clock cycle by comparing multiple symbol classes against multiple input symbols per cycle in parallel, signaling bundles of multiple transitions from parent cells to child cells and updating NFA state status by multiple steps. To retain high frequency operation, the cell array will not resolve transition chains from a first cell to a second cell to a third cell in a single cycle. When a chain is required, the cell array takes fewer steps in one cycle to break the chain into separate cycles. To detect multi-transition chains, each cell compares symbol classes to future symbols in advance and back-communicates future match positions to parent cells in the array as launch hazards.

Abstract: Disclosed is a method of recovering from overflow of a hardware dynamically reconfigurable NFA cell array, to find matches within a symbol stream to regular expression or similar rules without missing matches due to overflow. Upon overflow, active states are selected to spill from the cell array, saving state information and spill position. Scanning continues a limited distance, with additional overflow spills possible, to a selected end of segment position where all active end states are removed and recorded. A re-scan of the segment from the first overflow position begins with each previously spilled state re-injected at the same position it was spilled from. At the end of the segment, saved end states are re-injected and scanning continues. RE-scans may iterate if there was additional overflow. NFA states may be assigned color codes, with connected states receiving the same color, to aid in efficient overflow recovery.

Abstract: Disclosed is a hybrid architecture combining DFA and NFA based engines. The DFA engine and NFA engine scan the same input stream. The DFA engine may be a multi-threaded engine. Fragments of rules are assigned to the DFA engine and portions of rules are assigned to the NFA engine. Fragments matched by the DFA engine may be sorted by a sorter into NFA launch positions before activating NFA states. A dynamically reconfigurable NFA cell array may be used. An NFA state signaled by a DFA fragment match is loaded into NFA cell(s). The DFA fragments may be adjacent to start state positions or following high-branching NFA states. Look-around assertions may be used by the DFA to signal to the NFA to either prevent or permit continued matching of a rule.

Abstract: Disclosed is a method and system for matching a complex NFA state comprising a spinner followed by a character class sequence which may be represented by the general regular expression form [S] {N,M}[A0][A1] . . . [Ak?1]. An input transition activates the spinner and the spin count increments with successive matches of the spin class [S]. When the spin count is between N and M, sequence matching begins. Several base sequence CCLs are compared in parallel with a corresponding window of input symbols. If all match, a signal enters a delay line until the end of the base sequence. When the signal exits the delay line, extended sequence CCLs are accessed from a table sequentially and compared with successive input symbols. After the final extension CCL matches, an output transition is signaled. For short sequences, unused base sequence CCLs may be configured with look-ahead classes.

Abstract: Disclosed is a method of pre-fetching NFA instructions to an NFA cell array. The method and system fetch instructions for use in an L1 cache during NFA instruction execution. Successive instructions from a current active state are fetched and loaded in the L1 cache. Disclosed is a system comprising an external memory, a cache line fetcher, and an L1 cache where the L1 cache is accessible and searchable by an NFA cell array and where successive instructions from a current active state in the NFA are fetched from external memory in an atomic cache line manner into a plurality of banks in the L1 cache.

Abstract: Disclosed is a method and apparatus for pre-fetching child states in an NFA cell array. A pre-fetch depth value is determined for each transition in an NFA graph. The pre-fetch depth value is accessed for transition from an active state in the NFA graph. The child states of the active state are pre-fetched to the depth of the pre-fetch depth value recursively. A loader loads the pre-fetched states into the NFA cell array.

Abstract: Disclosed is method of matching a character class to a symbol of an input stream. A character class, or a plurality of character classes, is defined into an accessible format which when accessed is compared to a symbol in an input stream. The format may be stored in an NFA array cell or it may be broadcast to the cell array with an input symbol for comparison.

Abstract: In a hardware engine, finding rule matches within an input stream by executing a Nondeterministic Finite Automaton (NFA) with active states tracked in parallel cells, a Start Pointer (SP) is captured by the cell beginning a match and passed from cell to cell until the match completes, when it is reported by the cell ending the match. For multiple overlapping matches, different cells may hold different SPs, and a cell representing multiple NFA states may hold multiple SPs. Methods are given to select one SP when multiple SPs collide in the same state.

Abstract: Disclosed is a method for simultaneously finding matches for rules that require greedy matching and comprehensive matching by executing a single Deterministic Finite Automaton (DFA). DFAs annotations are used to enable a single DFA to represent rules that require greedy and comprehensive matching. DFA descents are performed from various positions in an input stream, match information is recorded and match results are selectively generated (filtered) to achieve the greedy or comprehensive match behavior required by individual rules.

Abstract: Disclosed is an architecture, system and method for performing multi-thread DFA descents on a single input stream. An executer performs DFA transitions from a plurality of threads each starting at a different point in an input stream. A plurality of executers may operate in parallel to each other and a plurality of thread contexts operate concurrently within each executer to maintain the context of each thread which is state transitioning. A scheduler in each executer arbitrates instructions for the thread into an at least one pipeline where the instructions are executed. Tokens may be output from each of the plurality of executers to a token processor which sorts and filters the tokens into dispatch order.

Abstract: Disclosed is a method and system of matching a string of symbols to a ruleset. The ruleset comprise a set of rules. The method includes ignoring begin anchor requirements when constructing a DFA from all the rules of the ruleset, annotating the accepting states of the DFA with the begin anchor information, executing the DFA, and checking begin anchor annotations to determine if begin anchor requirement are satisfied if an accepting state is reached. Embodiments also include rulesets with begin anchors on matches, rulesets with early exit information on non-accepting states, and rulesets with accept begin anchors in accepting states.

Abstract: A system and method for peripheral control. The present invention relates to utilizing device address call sequencing for control of active memory bus peripheral devices. To prevent problems inherent with triggering events in active memory bus peripherals, such as are associated with error correction means, and to minimize pin usage, a system and method are provided to utilize memory address call sequencing of other devices to trigger such events.