Patents by Inventor Michael Ruprecht

Michael Ruprecht has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11171474
    Abstract: In some examples, a device includes at least one input node configured to receive a signal indicating a current through a conductor to a load. The device also includes circuitry configured to determine a first magnitude of the received signal in a first frequency range by applying a first bandpass filter to the received signal. The circuitry is also configured to determine a second magnitude of the received signal in a second frequency range by applying a second bandpass filter to the received signal. The processing circuitry is further configured to determine that an electric arc has occurred on the conductor based on the first magnitude and the second magnitude.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: November 9, 2021
    Assignee: Infineon Technologies AG
    Inventors: Mihai-Alexandru Ionescu, Michael Asam, Louis Janinet, Michael Ruprecht, Redouane Djeghader
  • Publication number: 20210066904
    Abstract: In some examples, a device includes at least one input node configured to receive a signal indicating a current through a conductor to a load. The device also includes circuitry configured to determine a first magnitude of the received signal in a first frequency range by applying a first bandpass filter to the received signal. The circuitry is also configured to determine a second magnitude of the received signal in a second frequency range by applying a second bandpass filter to the received signal. The processing circuitry is further configured to determine that an electric arc has occurred on the conductor based on the first magnitude and the second magnitude.
    Type: Application
    Filed: August 27, 2019
    Publication date: March 4, 2021
    Inventors: Mihai-Alexandru Ionescu, Michael Asam, Louis Janinet, Michael Ruprecht, Redouane Djeghader
  • Patent number: 6603321
    Abstract: A method for determining the electromigration characteristics of a wiring structure in an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the method includes configuring a defined test structure type for the integrated circuit device. The defined test structure type further includes a first line of wiring primarily disposed in a principal plane of a semiconductor substrate, and a second line of wiring connected to the first line of wiring. The second line of wiring is disposed in a secondary plane which is substantially parallel to the principal plane, with the first and second lines of wiring being connected by a via structure therebetween. A thermal coefficient of resistance for the first line of wiring and the via structure is determined, and a wafer-level stress condition is introduced in a first individual test structure of the defined test structure type.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: August 5, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ronald G. Filippi, Jr., Alvin W. Strong, Timothy D. Sullivan, Deborah Tibel, Michael Ruprecht, Carole Graas
  • Publication number: 20030080761
    Abstract: A method for determining the electromigration characteristics of a wiring structure in an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the method includes configuring a defined test structure type for the integrated circuit device. The defined test structure type further includes a first line of wiring primarily disposed in a principal plane of a semiconductor substrate, and a second line of wiring connected to the first line of wiring. The second line of wiring is disposed in a secondary plane which is substantially parallel to the principal plane, with the first and second lines of wiring being connected by a via structure therebetween. A thermal coefficient of resistance for the first line of wiring and the via structure is determined, and a wafer-level stress condition is introduced in a first individual test structure of the defined test structure type.
    Type: Application
    Filed: October 26, 2001
    Publication date: May 1, 2003
    Applicant: International Business Machines Corporation and Infineon Technologies North America Corp.
    Inventors: Ronald G. Filippi, Alvin W. Strong, Timothy D. Sullivan, Deborah Tibel, Michael Ruprecht, Carole Graas
  • Patent number: 6492247
    Abstract: A method for manufacturing integrated circuits (“IC”) on wafers to manage crack damage in the ICs such that crack propagation into the IC active array is reduced or eliminated. The method provides for a defined separation or divide of the IC gate conductor from the IC crack stop or IC edge. The method is especially useful in managing crack damage induced through the delamination of one or more of the gate conductor surface interfaces as a result of the IC wafer dicing process. Circuits or chips manufactured according to the methods disclosed are also taught.
    Type: Grant
    Filed: November 21, 2000
    Date of Patent: December 10, 2002
    Assignee: International Business Machines Corporation
    Inventors: William H. Guthrie, Andreas Kluwe, Michael Ruprecht
  • Patent number: 6134241
    Abstract: In a telecommunication system, more particularly for the range of ISDN technology, which includes a switching device (1), a telecommunication terminal unit (19) coupled to the switching device (1) via a first number of bus lines (3, 4, 5, 6), and (9, 10, 11, 12) for providing phantom power supply to the telecommunication terminal unit (19) via the first number of bus lines (3, 4, 5, 6), user communication means including actuation switches (28) and indicator lamps (29) are coupled to the telecommunication terminal unit (19) via a second number of bus lines (14, 115, 16, 17). This enables simplified telecommunication with minimum circuitry and cost. Power is supplied to the communication means (28, 29) by the telecommunication terminal via the second number of bus lines (14, 15, 16, 17).
    Type: Grant
    Filed: November 6, 1996
    Date of Patent: October 17, 2000
    Assignee: U.S. Philips Corporation
    Inventor: Michael Ruprecht