Abstract: An envelope detector comprises a first differential transistor pair that receives first and second input signals, a second differential transistor pair that receives third and fourth input signals, a resistor, a current source, and a comparator. The first and second differential pairs each comprise two transistors having first current terminals coupled together and second current terminals coupled together. The resistor is coupled between the second current terminals of the first and second differential pairs. The current source has a first terminal coupled to the second terminal of the resistor and to second current terminals of the second differential pair and a second terminal configured to receive a negative supply voltage. The comparator has a negative input coupled to first current terminals of the first differential pair and a positive input coupled to first current terminals of the second differential pair.

Abstract: A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a particular duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.

Abstract: A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a predetermined duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.

Abstract: A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a predetermined duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.

Abstract: In an example, a circuit includes a first power switch device coupled between a voltage input and an output terminal, the first power switch device having a control input. A voltage divider circuit includes a first resistor and a second resistor. The first resistor is coupled between the voltage input and a sense node between the first resistor and the second resistor. The second resistor has a first terminal coupled to the sense node and a second terminal. A second switch device is coupled between the second terminal of the second resistor and an electrical ground terminal. A voltage clamp is coupled between the sense node and the electrical ground terminal.

Abstract: In an example, a circuit includes a first power switch device coupled between a voltage input and an output terminal, the first power switch device having a control input. A voltage divider circuit includes a first resistor and a second resistor. The first resistor is coupled between the voltage input and a sense node between the first resistor and the second resistor. The second resistor has a first terminal coupled to the sense node and a second terminal. A second switch device is coupled between the second terminal of the second resistor and an electrical ground terminal. A voltage clamp is coupled between the sense node and the electrical ground terminal.

Abstract: Described examples include a semiconductor device having a resistor. The resistor includes a first terminal and a second terminal. The resistor also includes a first resistive element over an insulating layer over a substrate having a first end coupled to the first terminal of the resistor and a second end coupled to the second terminal of the resistor; and a parallel second resistive element over the insulating layer over the substrate having a first end coupled to the first terminal of the resistor and a second end coupled to the second terminal of the resistor. The resistor may also be coupled in series with another resistor.

Abstract: Described examples include a semiconductor device having a resistor. The resistor includes a first terminal and a second terminal. The resistor also includes a first resistive element over an insulating layer over a substrate having a first end coupled to the first terminal of the resistor and a second end coupled to the second terminal of the resistor; and a parallel second resistive element over the insulating layer over the substrate having a first end coupled to the first terminal of the resistor and a second end coupled to the second terminal of the resistor. The resistor may also be coupled in series with another resistor.

Abstract: Peak detection methods, apparatus, and circuits are disclosed. An example peak detector includes a first peak-hold circuit having a first input terminal and a first output terminal, the first peak-hold circuit to determine a first peak of a rectified input voltage at the first input terminal during a first time interval, and to track a second peak of the rectified input voltage during a second time interval, the second time interval distinct from the first time interval, and a second peak-hold circuit having a second input terminal and a second output terminal, the second peak-hold circuit to determine, during the second time interval, a greater of the first peak and the second peak, the first output terminal coupled to the second input terminal, the greater of the first peak and the second peak output at the second output terminal.

Abstract: Peak detection methods, apparatus, and circuits are disclosed. An example peak detector includes a first peak-hold circuit having a first input terminal and a first output terminal, the first peak-hold circuit to determine a first peak of a rectified input voltage at the first input terminal during a first time interval, and to track a second peak of the rectified input voltage during a second time interval, the second time interval distinct from the first time interval, and a second peak-hold circuit having a second input terminal and a second output terminal, the second peak-hold circuit to determine, during the second time interval, a greater of the first peak and the second peak, the first output terminal coupled to the second input terminal, the greater of the first peak and the second peak output at the second output terminal.

Abstract: A power factor correction (PFC) integrated circuit having a feed forward circuit. The feed forward circuit comprises a first current source, a second current source, and a third current source, a first bi-polar junction transistor (BJT), a second BJT, a third BJT, and a fourth BJT coupled together in a translinear cell, where the first current source is coupled to the first BJT, the second current source is coupled to the second BJT, and the third current source is coupled to the third BJT, a biasing network coupled to the first BJT and to the second BJT and configured to maintain equal collector-to-emitter voltage across the first BJT and the second BJT, where the feed forward circuit is configured to output a current based on a current of the first current source, a current of the third current source, and a current of the second current source.

Abstract: A current mirror includes a first pair of transistors, wherein gates of the first pair of transistors are connected together, and a second pair of transistors coupled to the first pair of transistors. Gates of the second pair of transistors are connected together. A first resistive device is coupled across a drain and a source of one of the transistors of the second pair of transistors. A second resistive device is coupled across a drain and a source of the other transistor of the second pair of transistors. The first pair of transistors are configured to operate in weak inversion at an input current to the current mirror within a first current range and the second pair of transistors are configured to operate in strong inversion at an input current within a second current range.

Abstract: At least some aspects of the present disclosure provide for a circuit. In one example, the circuit includes a logic circuit having multiple inputs and multiple outputs, a calculated discontinuous conduction (DCM) (TDCM) timer having an input coupled to one of the logic circuit outputs and an output coupled to one of the logic circuit inputs, an on-time (TON) timer having an input coupled to one of the logic circuit outputs and an output coupled to one of the logic circuit inputs, and a hysteresis timer having an input coupled to one of the logic circuit outputs and multiple outputs coupled to multiple of the logic circuit inputs.