Abstract: Apparatus and methods for regulating methanol concentration in a direct methanol fuel cell system without the need for a methanol concentration sensor. One or more operating characteristics of the fuel cell, such as the potential across the load, open circuit potential, potential at the anode proximate to the end of the fuel flow path or short circuit current of the fuel cell, are used to actively control the methanol concentration.

Abstract: Apparatus and methods for regulating methanol concentration in a direct methanol fuel cell system without the need for a methanol concentration sensor. One or more operating characteristics of the fuel cell, such as the potential across the load, open circuit potential, potential at the anode proximate to the end of the fuel flow path or short circuit current of the fuel cell, are used to actively control the methanol concentration.

Abstract: For a direct oxidation fuel cell system in which the source fuel is diluted with a diluting fluid prior to entering the fuel cell generally, and for a Direct Methanol Fuel Cell System (DMFC) in which the methanol source fuel is diluted with water, the dielectric constant of the fuel mix comprising the source fuel and the diluting fluid is measured to determine the relative proportions of source fuel and diluting fluid within this fuel mix. This measurement may then be used in a feedback loop to control the subsequent mixing of the source fuel with the diluting fluid, and in particular, to adjust the mix in the event the fuel mix is too rich or too dilute as compared to a desired mixing proportion. Additionally, a second dielectric constant measurement is used to determine the source fuel level of a fuel tank providing source fuel to the fuel cell. Finally, an optional telecommunications link is used to automatically order a source fuel refill when the source fuel runs low.

Abstract: Apparatus and methods for regulating methanol concentration in a direct methanol fuel cell system are provided. The apparatus and methods do not require a methanol concentration sensor. One or more operating characteristics of the fuel cell, such as the potential across the load, open circuit potential or potential at the anode proximate to the end of the fuel flow path, are used to actively control the methanol concentration.

Abstract: Apparatus and methods for regulating methanol concentration in a direct methanol fuel cell system without the need for a methanol concentration sensor. One or more operating characteristics of the fuel cell, such as the potential across the load, open circuit potential, potential at the anode proximate to the end of the fuel flow path or short circuit current of the fuel cell, are used to actively control the methanol concentration.

Abstract: MOSFET-gated bipolar transistor and thyristor integrated devices combining, as the respective turn-on and turn-off control devices, an enhancement mode MOSFET and a depletion mode MOSFET. The gates of the two MOSFETs are connected to a single device gate terminal. The conduction channel of the depletion mode MOSFET is preferably an implanted region. With gate voltage of appropriate polarity applied, the depletion mode MOSFET is non-conducting and the enhancement mode MOSFET is conducting, biasing the included bipolar transistor or thyristor into conduction. With zero gate voltage applied, the depletion mode MOSFET conducts and the enhancement mode MOSFET is non-conducting, turning off the included bipolar transistor or thyristor. Significantly, only a single polarity gate input signal is required.

Abstract: The present invention relates generally to insulated gate transistors and more particularly, to laterally implemented insulated gate transistors having improved current capacity and improved immunity to latch-up. Specifically, it has been found that a lateral insulated gate transistor fabricated on a heavily doped substrate such as a p+ substrate exhibits improved current density. Further, the inclusion of an additional heavily doped region such as a P+ region proximate the base region contributes to improved latch-up immunity within the device.

Abstract: Premature avalanche breakdown resulting from high electric fields produced by metal interconnections crossing underlying high conductivity regions of an integrated circuit is eliminated by selectively providing discontinuities in the high conductivity regions underlying the metal interconnection paths.

Abstract: An integrated circuit in which a large potential can be maintained between the source of the device and the substrate on which this device and other devices are fabricated is described. The circuit employs a minority carrier sink region to remove minority carriers from the gate region of a MOS depletion device. The sink region is shielded from the substrate by a buried layer which prevents punch-through between the sink region and the substrate.

Abstract: An integrated circuit with a substrate of one conductivity type and a drift layer on the substrate of opposite conductivity type includes a high voltage semiconductor device, such as a P-N diode, with a first main device region of the opposite conductivity type adjoining the drift layer and a second main device region of the same conductivity type as the substrate adjoining the drift layer. The high voltage semiconductor device is electrically isolated from other devices through the incorporation into the integrated circuit of an isolation region adjoining the substrate and surrounding the high voltage device. Electrical isolation of the high voltage device from the substrate is achieved by interposing a highly-doped buried layer of the opposite conductivity type between the second main device region and the substrate so as to prevent current carrier injection from the second main device region into the substrate.

Abstract: A switch is provided wherein a piezoelectric bimorph element is used to provide many separately controllable, closely spaced switchable contacts. The element includes at least two oppositely extending fingers connected by a common spine. The element spine is mounted to a case with the fingers spaced from an inner case surface. Electronic circuit means are mounted on the element spine for applying a separate electrical potential to each of the element fingers. A separate movable electrical contact is disposed on each of the element fingers spaced from the spine and insulated from the means for applying the separate electrical potentials to the fingers. A separate stationary contact is provided on an inner case surface opposite each of the movable contacts. In operations, a separate electrical potential is applied to each of the element fingers for selectively causing each finger to deflect and force its movable contact into electrical connection with the opposing stationary contact.

Abstract: A switch is provided wherein a piezoelectric bimorph element is used to provide many separately controllable, closely spaced switchable contacts. The element includes at least two oppositely extending fingers connected by a common spine. The element spine is mounted to a case with the fingers spaced from an inner case surface. Electronic circuit means are mounted on the element spine for applying a separate electrical potential to each of the element fingers. A separate movable electrical contact is disposed on each of the element fingers spaced from the spine and insulated from the means for applying the separate electrical potentials to the fingers. A separate stationary contact is provided on an inner case surface opposite each of the movable contacts. In operation, a separate electrical potential is applied to each of the element fingers for selectively causing each finger to deflect and force its movable contact into electrical connection with the opposing stationary contact.

Abstract: A solid state composite control circuit includes a normally-off gating device connected in series with a normally-on high voltage semiconductor device so that the combination operates as a normally-off high power semiconductor device. The control device is a low voltage semiconductor device, which can switch rapidly with very low gate turn-off current during turn-off of the composite circuit. In a particular example, a low voltage, normally-off, MOSFET is connected in series with the cathode of a high voltage, normally-on FCT. In another example, a low voltage, normally-off, MOSFET is connected in series with the source of a high voltage, normally-on JFET. The composite circuit has a very high turn-off gain as well as high dv/dt and di/dt capability.

Abstract: Power MOSFET devices useful in synchronous rectifier circuit applications are bidirectional and symmetrical for use in AC circuits, and have low on-resistance, fast switching speed, and high voltage capability. In one embodiment, a planar enhancement-mode diffused MOSFET structure obviates the source-to-base short conventionally included to prevent turn-on of the parasitic bipolar transistor defined by the main terminal regions of one conductivity type and the intermediate base region of opposite conductivity type, by employing within the base region a recombination region having a relatively small lifetime for excess base region majority-carriers in order to inhibit operation of the parasitic bipolar transistor. Another embodiment resembles a pair of conventional, vertical-current, MOSFET unit cells formed symmetrically back-to-back and sharing a common drain region which serves only as an intermediate terminal region not directly connected to any device terminal.

Abstract: Fabrication of an integrated circuit containing complementary, dielectrically-isolated, high voltage semiconductor devices of the lateral-current conduction type involves doping of the voltage-supporting regions of the complementary devices in two steps, in accordance with Lateral Charge Control technology. A first conductivity type dopant is introduced into a semiconductor layer as it is being epitaxially grown, with the dopant concentration being below about 20 percent of the desired final doping concentration of the first conductivity type voltage-supporting region. Ion implantation of further first conductivity type dopant achieves final doping of the first conductivity type voltage-supporting region, while a separate ion implantation of a second conductivity dopant achieves final doping of the second conductivity type voltage-supporting region.

Abstract: A beam-addressed memory system for digital memory recording and reading which comprises an electron beam generating and focusing subsystem, an electron detecting subsystem, electronic control and interface circuit means, and a storage medium consisting essentially of a cross-linkable polymeric film having an implanted surface layer of heavy metal ions.

Abstract: A P-N diode includes a P.sup.- substrate with a thin N.sup.- epitaxial layer thereon. A P.sup.+ isolation region surrounds the periphery of the N.sup.- epitaxial layer and is integrally connected to the P.sup.- substrate. An N.sup.+ cathode region extends into the N.sup.- epitaxial layer from the upper surface of such layer. A P.sup.+ anode region extends into the N.sup.- epitaxial layer from its upper surface and surrounds the N.sup.+ cathode region. A further P.sup.+ region extends into the N.sup.- epitaxial layer from its upper surface and surrounds the N.sup.+ cathode region, and, in turn, is surrounded by the P.sup.+ anode region. The further P.sup.+ region is biased at the same potential as the P.sup.- substrate. An N.sup.+ buried layer is situated between the P.sup.- substrate and the N.sup.- epitaxial layer, beneath the P.sup.+ anode region, and surrounds the N.sup. + cathode region. An N.sup.+ sinker region extends into the N.sup.

Abstract: A semiconductor device, such as a MOSFET or IGR, is fabricated with a base region having a deep portion for reducing parasitic currents. A wafer is provided having an N type layer on an appropriately doped substrate. A first oxide layer is formed on the wafer, and a refractory electrode layer is deposited on the first oxide layer. A first window is opened in the refractory electrode layer, and then silicon nitride is deposited on the wafer. A second window is opened in the silicon nitride layer, within the first window. A deep P.sup.+ base region is diffused into the wafer through the second window, and then a second oxide layer is selectively grown in the second window. The silicon nitride layer is selectively removed, thereby opening a third window, defined by the second window and the second oxide layer situated within the second window. A shallow P base region is diffused into the wafer through the third window, followed by diffusion of a shallow N.sup.+ region through the third window.

Abstract: Apparatus facilitating the switching and control of the power consumption level of at least one power-consuming load remotely located from a central facility. Load switching and power-consumption control commands are sent from the central facility to each of the remote locations to provide an analog signal having a programmable amplitude or programmable pulse-width thereof to an intelligent load control and switching circuit. The load control and switching circuit not only controls the coupling of a power source to a power-consuming load, but also controls the portion of the source waveform cycle during which the load is coupled to the source, to control the average power consumption thereof. Several embodiments of load control and switching circuitry, as well as power supplies for providing operating potential thereto, are disclosed.

Abstract: A semiconductor device for operation at high switching speeds includes a region of reduced carrier lifetime situated in the portion of the device in which the peak amount of carrier recombination occurs during device turn-off. This region of reduced carrier lifetime causes fast carrier recombination during device turn-off such that device switching speed is correspondingly increased over that of comparable conventional devices.