Abstract: A bus interface unit is provided for a digital signal processor including a core processor, a memory and two or more system buses for transfer of data to and from system components. The bus interface unit includes a first bus controller for receiving processor transfer requests from the core processor on two or more processor buses and for directing the processor transfer requests to the memory on a first memory bus. The bus interface further includes a second bus controller for receiving system transfer requests from the system components on the two or more system buses and for directing the system transfer requests to the memory on a second memory bus. The bus controllers may have pipelined architectures and may be configured to service transfer requests independently.

Abstract: Methods and apparatus are provided for supplying data to a processor in a digital processing system. The method includes holding data required by the processor in a chache memory, supplying data from the cache memory to the processor in response to processor requests, performing a cache line fill operation in response to a chache miss, supplying data from a prefetch buffer to the cache memory in response to the cache line fill operation, and speculatively loading data from a lower level memory to the prefetch buffer in response to the cache line fill operation.

Abstract: A memory system and a method for operating a memory system are provided. The memory system includes a set of memory banks, logic for calculating a first address in each memory bank from the set of memory banks and a controller receiving a transfer address from a computing device. The controller includes logic for selecting a memory bank from the set of memory banks based on the transfer address and the first addresses of the memory banks, and for mapping the transfer address to a target address in the selected memory bank based on a first address in the selected memory bank. As a result, the set of memory banks has a contiguous memory space.

Abstract: A note stacker for a currency validator includes a stationary punch and movable rails having slots therein adapted for receiving the currency tendered thereto. The stationary punch comprises a top plate surface of the housing maintaining drive motors and gears of the stacker itself. The top plate is curved to accommodate the natural deflection of the bill as it is being stacked, and is provided with a durable frictional material along lateral edges thereof to prevent the bill from sliding or otherwise moving upon the surface of the curved plate. A leading edge of the curved plate is provided with serrations or teeth which, in conjunction with a shutter fixed to the movable rails, serves to defeat strings or other retrieval elements.

Abstract: The invention provides partially purified EPS that was purified from Thauera sp. Strain MZ1T. This partially purified EPS comprises rhamnose, xylose, galacturonic acid, galactose, glucose, N-acetylfucosamine. The invention further provides methods of producing the partially purified EPS and of utilizing the partially purified EPS in methods of chelating metals. Further provided by this invention is an exopolysaccharide termed “thaueran” that was purified from Thauera sp. Strain MZ1T. This exopolysaccharide has a molecular weight of about 250 kDa and comprises rhamnose, galacturonic acid, N-acetylfucosamine and N-acetylglucosamine. The invention also provides methods of producing the exopolysaccharide and of utilizing the exopolysaccharide in methods of chelating metals.

Abstract: A note stacker for a currency validator includes a stationary punch and movable rails having slots therein adapted for receiving the currency tendered thereto. The stationary punch comprises a top plate surface of the housing maintaining drive motors and gears of the stacker itself. The top plate is curved to accommodate the natural deflection of the bill as it is being stacked, and is provided with a durable frictional material along lateral edges thereof to prevent the bill from sliding or otherwise moving upon the surface of the curved plate. A leading edge of the curved plate is provided with serrations or teeth which, in conjunction with a shutter fixed to the movable rails, serves to defeat strings or other retrieval elements.

Abstract: The invention relates to a process for preparing quinoline-substituted carbonate and carbamate compounds, which are important intermediates in the synthesis of 6-O-substituted macrolide antibiotics. The process employs metal-catalyzed coupling reactions to provide a carbonate or carbamate of formula (I) or (II) or a substrate that can be reduced to obtain the same.

Abstract: A digital baseband processor is provided which receives a system clock generated by a system oscillator and generates a plurality of clock signals from the system clock. The digital baseband processor includes a digital signal processor for executing digital signal processor instructions, a microcontroller for executing microcontroller instructions, and other modules which may require one of the plurality of clock signals for operation. The digital baseband processor also includes a power management circuit which may power down the system oscillator when modules such as the digital signal processor and microcontroller do not require clock signals derived from the system oscillator. The power management circuit may gate off clock signals to modules when those modules do not require clock signals, without powering down the system oscillator.

Abstract: The invention relates to a process for preparing quinoline-substituted carbonate and carbamate compounds, which are important intermediates in the synthesis of 6-O-substituted macrolide antibiotics. The process employs metal-catalyzed coupling reactions to provide a carbonate or carbamate of formula (I) or (II) or a substrate that can be reduced to obtain the same.

Abstract: Methods and apparatus for accessing flash memory in a continued burst mode are provided. The apparatus includes a processor for executing instructions including memory access instructions, the processor generating a next access signal that indicates if a next memory access is in sequence with a current memory access, a memory having a continued burst mode of operation, and a bus interface for controlling access to the memory in response to the memory access instructions. The bus interface unit enables the continued burst mode of the memory while the next access signal is asserted.

Abstract: Methods and apparatus are provided for operating an embedded processor system that includes a processor and a cache memory. The method includes filling one or more lines in the cache memory with data associated with a first task, executing the first task, and, in response to a cache miss during execution of the first task, performing a cache line fill operation and, during the cache line fill operation, executing a second task. The cache memory may notify the processor of the line fill operation by generating a processor interrupt or by notifying a task scheduler running on the processor.

Abstract: The invention relates to a process for preparing quinoline-substituted carbonate and carbamate compounds, which are important intermediates in the synthesis of 6-O-substituted macrolide antibiotics. The process employs metal-catalyzed coupling reactions to provide a carbonate or carbamate of formula (I) or (II) or a substrate that can be reduced to obtain the same.

Abstract: In parallel with accesses to a cache made by a core processor, a DMA controller is used to pre-load data from a main memory into the cache. In this manner, the pre-load function can make the data available to the processor application before the application references the data, thereby potentially providing a 100% cache hit ratio since the correct data is pre-loaded into the cache. In addition, if a copy-back cache is employed, the cache memory system can also be configured such that processed data can be dynamically unloaded from the cache to the main memory in parallel with accesses to the cache made by the core processor. The pre-loading and/or post unloading of data may be accomplished, for example, by using a DMA controller to burst data into and out of the cache in parallel with accesses to the cache by the core processor. This DMA control function may be integrated into the existing cache control logic so as to reduce the complexity of the cache hardware (e.g.

Abstract: After one way of an associative cache is disabled from the perspective of a core processor, a DMA data transfer operation may be commenced to pre-load data into the disabled way from a main memory or to unload data from the disabled way into the main memory. By using a separate decoder for each way of the cache, a few additional multiplexers, and additional control circuitry, different ways of a cache may be accessed concurrently by the core processor and the DMA controller. Therefore, while a DMA transfer operation takes place with respect to the disabled way of the cache, the other ways of the cache remain accessible by the core processor. By properly pre-loading and unloading data from selected ways of the cache in this manner, the cache hit ratio by the core processor can approach 100%.

Abstract: The invention relates to a process for preparing quinoline-substituted carbonate and carbamate compounds, which are important intermediates in the synthesis of 6-O-substituted macrolide antibiotics. The process employs metal-catalyzed coupling reactions to provide a carbonate or carbamate of formula (I) or (II) or a substrate that can be reduced to obtain the same.

Abstract: The invention relates to a process for preparing quinoline-substituted carbonate and carbamate compounds, which are important intermediates in the synthesis of 6-O-substituted macrolide antibiotics. The process employs metal-catalyzed coupling reactions to provide a carbonate or carbamate of formula (I) or (II) or a substrate that can be reduced to obtain the same.

Abstract: An improved replaceable liquid application system for applying a liquid intermediate transfer surface to a support surface in a printer is provided. The liquid application system is contained in a removable cassette and utilizes a liquid impregnated arcuate surface that engages the support surface by rolling contact. The liquid impregnated arcuate surface and a reclamation assembly are contained in a removable cartridge in the cassette. A cartridge life status assembly determines when the useful life of the cartridge has been exhausted. Push tabs on the cartridge and finger wells on the cassette allow for easy and convenient removal of a used cartridge and insertion of a replacement cartridge.

Abstract: The present invention discloses a process for the preparation of a hydroxymethylthiazole compound having formula 3: The process of the invention comprises reacting a halomethyl thiazole having the formula: ##STR1## with water, at an elevated temperature. Optionally, the reaction can be carried out in the presence of a base, such as sodium carbonate, which can react with any acid formed. In the process of the invention, X is a halogen atom; and R.sup.6 is selected from the group consisting of hydrogen, and halogen atoms. The invention also contemplates the preparation of acid addition salts of the hydroxymethylthiazole, compound 3.

Abstract: A system and a method for providing farmers/producers with crop characteristic predictions for standing crops located in fields includes a central database for storing field and crop information for the crops. A weather data processor receives raw weather data from either or both of (1) a weather data service with collected weather data from a plurality of weather stations; and (2) one or more site-specific weather stations associated with a particular field whose information is in the database. The raw weather data are processed to obtain field weather parameters for entry into a crop characteristic prediction equation, and the parameters are stored in the central database. With a user interface, a crop whose information is stored in the central database is selected.

Abstract: The present invention provides a system and method for efficient execution of load reserve (LARX) and store conditional (STCX) instructions in a superscalar processor. A system for efficiently providing a LARX instruction in a superscalar processor is disclosed. The system comprises a data cache (Dcache) for receiving the LARX instruction. The data cache further includes a decoder means for setting and resetting of a validation of the load reserve instruction, an internal cache for receiving address information and for providing data. The system also includes a register means for receiving the LARX instruction and a controller means for providing a physical address based upon the address information. The system provides for the validation being accomplished in one cycle for the LARX instruction when there is a hit on the internal data cache.