Abstract: A reset detector is disclosed, which monitors the hardware reset of the subsystem(s) involved, in order to verify that the hardware reset has placed the subsystem in a correct reset state. Thus, in order to verify that an initial hardware reset has occurred, the subsystem software (e.g., during boot-up) detects the initial reset status of the reset detector, and blocks any additional reset attempts that may occur. In other words, the reset detector verifies that the subsystem hardware has been reset correctly, before the application software can proceed into an operational mode. An example reset detector circuit is disclosed, which includes a local reset signal generated by an RC delay circuit. The local reset signal is isolated from the system reset function, which allows the reset detector circuit to be initialized and reset separately from the system reset. Once the reset detector circuit is initialized, it monitors the system reset request line.