Abstract: A switched capacitor controller accurately controls the rise time of an on-chip generated high voltage. An on-chip charge pump is used to generate a high voltage (VPP) from an external power supply voltage (VCC). This high voltage signal (VPP) can be used to program Flash memory cells. A capacitor of a switched capacitor circuit is selectively switched between ground and a given node voltage. This generates a stair-stepped ramp function. The period of the steps is controlled according to a clock signal. This clock signal may be altered to produce the desired period. The voltage increases of the steps is regulated by a reference voltage multiplied by a ratio between two capacitor values. Thereby, the rise-time of the ramp function is accurately controlled as a function of the frequency of the clock signal and the ratio of the two capacitor values.

Abstract: A system is disclosed for producing an indication of the logical state of a flash memory cell for virtual ground flash memory operations. The system comprises a bit line charge and hold circuit which is operable to apply a read sense voltage (e.g., about 1.2 volts) to a bit line associated with the drain terminal of a cell of the flash array adjacent to the cell which is sensed, wherein the applied drain terminal voltage is substantially the same as the cell sense voltage (e.g., about 1.2 volts) applied to the drain terminal bit line of the selected memory cell to be sensed.

Abstract: The present invention relates to flash memory systems and methods to determine the threshold voltage of core cells. In one exemplary system, there is provided a method of characterizing the high end of the threshold voltage distribution of an array of programmed cells. In accordance with the invention, an exemplary system and method are presented to apply a varying characterization signal operably through a high breakdown voltage periphery donut transistor and wordline drive transistors, which are driven into saturation by a boosted gate voltage which is higher than the applied varying characterization signal, in a manner which provides for the accurate determination of the VT of the core cells, through the comparison of the conduction in a reference cell to that of the conduction in a core cell produced by a varying characterization signal applied to the core cell gate.

Abstract: A technique to determine whether multiple memory cells are programmed or erased. After a program or erase operation, respective program or erase verify operations are performed. A logical gate is coupled to measure the state of each memory cell. When all memory cells selected to be programmed or erased are programmed or erased then the output of the logical gate indicates successful program or erase verify. Thus, by using a single logical gate coupled to measure the states of multiple memory cells, only the output of the logical gate need be measured to determine successful program or erase verification of multiple memory cells.

Abstract: The present invention is a power-on reset circuit that generates a precise power-on reset pulse with an upper threshold voltage that is highly insensitive to variations in temperature and integrated circuit fabrication processes. The power-on reset circuit of the present invention includes a self-biased current generator capable of receiving a supply voltage and generating a first current, which is proportional to an absolute temperature, in response to receiving the supply voltage. The power-on reset circuit of the present invention also includes a base-emitter voltage detector that is coupled to the self-biased current generator such that a second current flowing though the base-emitter voltage detector is substantially equal to the first current generated by the self-biased current generator.

Abstract: A non-volatile memory device includes a plurality of MOS transistors 34 and 36 connected to respective word lines 16 and 18 to allow individual pages of memory stored in the memory cells 8a, 10a and 8b, 10b on the respective word lines 16 and 18 to be erased and erase verified. A method of erasing a page of memory cells includes the steps of applying an erase voltage to one of the MOS transistors 16 and 18 to erase the page of memory cells along the respective word line, and applying an initial erase-inhibit floating voltage to other MOS transistors which are connected to the word lines unselected for page erase. In an erase verify mode, an erase verify voltage is applied to the word line which was selected for page erase in the erase mode, and an erase verify unselect voltage is applied to the word lines which was not selected for page erase.

Abstract: In the programming of a non-volatile memory device, such as a NAND flash memory device 100, a positive bias voltage V.sub.bias is applied to a bit line 44 to set a respective memory gate 44a in a programmed state. In a further embodiment, the positive bias voltage V.sub.bias is obtained by dividing the select drain gate voltage V.sub.cc using two resistors 56 and 58 connected in series.

Abstract: A precision power-on reset circuit which is highly insensitive to temperature and process variations includes a self-biased proportional-to-absolute-temperature (PTAT) current generator 4, a base-emitter (V.sub.BE) voltage detector 6, and a bipolar complementary metal oxide semiconductor (BiCMOS) inverter 8, which generates a power-on reset pulse for resetting an application circuit when a power supply voltage is turned on. The power-on reset circuit may further include a complementary metal oxide semiconductor (CMOS) buffer 10 coupled to the BiCMOS inverter 8 to isolate the application circuit from currents in the power-on reset circuit.

Abstract: A recursive voltage booster circuit is provided for generating a boosted output voltage to be higher than the low power supply potential to drive control gates via row decoder circuits and wordlines in an array of Flash EEPROM memory cells during a Read mode of operation. The voltage booster circuit includes a plurality of recursively connected boosting stages. The lower power supply potential has a voltage of +2.0 volts or lower. The boosted output voltage is significantly higher than what is traditionally available so as to enable reading of Flash EEPROM memory cells in a very low power supply voltage environment.