Patents by Inventor Michael S. Chung

Michael S. Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Precharging scheme for reading a memory cell
    Patent number: 6771543
    Abstract: A method of reading a memory cell, and a memory array using the method, are described. An electrical load is applied to a first node in the memory array, the first node corresponding to the memory cell. A second node in the memory array, the second node on a same word line as the first node, is precharged. The second node is separated from the first node by at least one intervening node in the same word line.
    Type: Grant
    Filed: August 22, 2002
    Date of Patent: August 3, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Keith Wong, Pau-Ling Chen, Michael S. Chung
  • Precharging scheme for reading a memory cell
    Publication number: 20040037137
    Abstract: A method of reading a memory cell, and a memory array using the method, are described. An electrical load is applied to a first node in the memory array, the first node corresponding to the memory cell. A second node in the memory array, the second node on a same word line as the first node, is precharged. The second node is separated from the first node by at least one intervening node in the same word line.
    Type: Application
    Filed: August 22, 2002
    Publication date: February 26, 2004
    Inventors: Keith Wong, Pau-Ling Chen, Michael S. Chung
  • Array VSS biasing for NAND array programming reliability
    Patent number: 5978266
    Abstract: A method is provided for biasing a NAND array EEPROM during programming to allow the array to be scaled down further before reach punchthrough. The sources of the ground-select transistors of the NAND array are biased at V.sub.cc instead of ground to reduce the voltage drop across the source and drain of the ground-select transistors. As a result, the channel length of the ground-select transistors can be further shortened before punchthrough is obtained, resulting in a higher density EEPROM.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: November 2, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Pau-ling Chen, Shane C. Hollmer, Binh Q. Le, Michael S. Chung
  • IC chip with noise suppression circuit
    Patent number: 4585958
    Abstract: A microprocessor chip is adapted to maintain its databus at a reference voltage level during idle times between outputs. The arrangement enables like pull-up and pull-down delays as well as low noise levels to be achieved in the output circuits.
    Type: Grant
    Filed: December 30, 1983
    Date of Patent: April 29, 1986
    Assignee: AT&T Bell Laboratories
    Inventors: Michael S. Chung, Masakazu Shoji