Patents by Inventor Michael S. Cranmer
Michael S. Cranmer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10002835Abstract: A semiconductor device and a stacked pillar used to interconnect a first semiconductor die and a second semiconductor die are provided. The semiconductor device has a substrate, a splice interposer, a first semiconductor die, a second semiconductor die and first to fourth plurality of pillars. The first to fourth plurality of pillars and the splice interposer form interconnection and wiring between the first semiconductor die, the second semiconductor die and the substrate. The stacked pillar has a first conductor layer formed on a surface of the first semiconductor die, a first solder layer formed on the first conductor layer, a second conductor layer formed on the first solder layer, and a second solder layer formed on the second conductor layer. The second solder layer is heat-reflowable to attach the stacked pillar to a surface of the second semiconductor.Type: GrantFiled: February 8, 2017Date of Patent: June 19, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Benjamin V. Fasano, Michael S. Cranmer, Richard F. Indyk, Harry Cox, Katsuyuki Sakuma, Eric D. Perfecto
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Patent number: 9953900Abstract: Device structures involving a conductor-filled via or trench, methods of forming such device structures, and methods of operating such device structures. A doped region is formed in the substrate. An opening, such as a via or trench, is formed that extends through the doped region and into a portion of the substrate beneath the doped region. A conductive plug in formed in the opening to provide the conductor-filled via or trench. The opening is positioned and dimensioned relative to a position and dimensions of the doped region to divide the doped region into a first section and a second section that is disconnected from the first section by the opening.Type: GrantFiled: March 29, 2016Date of Patent: April 24, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: John M. Safran, Sami Rosenblatt, Michael S. Cranmer, Chandrasekharan Kothandaraman
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Publication number: 20170287812Abstract: Device structures involving a conductor-filled via or trench, methods of forming such device structures, and methods of operating such device structures. A doped region is formed in the substrate. An opening, such as a via or trench, is formed that extends through the doped region and into a portion of the substrate beneath the doped region. A conductive plug in formed in the opening to provide the conductor-filled via or trench. The opening is positioned and dimensioned relative to a position and dimensions of the doped region to divide the doped region into a first section and a second section that is disconnected from the first section by the opening.Type: ApplicationFiled: March 29, 2016Publication date: October 5, 2017Inventors: John M. Safran, Sami Rosenblatt, Michael S. Cranmer, Chandrasekharan Kothandaraman
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Publication number: 20170148737Abstract: An interposer structure and a method of interconnecting first and second semiconductor dies are provided. A splice interposer is attached to a top surface of a substrate through a first plurality of pillars formed on a bottom surface of the splice interposer. The first semiconductor die is attached to the top surface of a substrate through a second plurality of pillars formed on a bottom surface of the first semiconductor die. The first semiconductor die is attached to a top surface of the splice interposer through a third plurality of pillars formed on the bottom surface of the first semiconductor. The height of the second plurality of pillars is greater than the height of the third plurality of pillars. The second semiconductor die is attached to the top surface of the splice interposer through a fourth plurality of pillars formed on a bottom surface of the second semiconductor die.Type: ApplicationFiled: February 8, 2017Publication date: May 25, 2017Applicant: GLOBALFOUNDRIES INC.Inventors: Benjamin V. FASANO, Michael S. CRANMER, Richard F. INDYK, Harry COX, Katsuyuki SAKUMA, Eric D. PERFECTO
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Patent number: 9607973Abstract: A method of interconnecting first and second semiconductor dies is provided. A splice interposer is attached to a top surface of a substrate through first pillars formed on a bottom surface of the splice interposer. The first semiconductor die is attached to the top surface of a substrate through second pillars formed on a bottom surface of the first semiconductor die. The first semiconductor die is attached to a top surface of the splice interposer through third pillars formed on the bottom surface of the first semiconductor. The second semiconductor die is attached to the top surface of the splice interposer through fourth pillars formed on a bottom surface of the second semiconductor die. The first to fourth plurality of pillars and the splice interposer form interconnection and wiring between the first semiconductor die, the second semiconductor die and the substrate.Type: GrantFiled: November 19, 2015Date of Patent: March 28, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Benjamin V. Fasano, Michael S. Cranmer, Richard F. Indyk, Harry Cox, Katsuyuki Sakuma, Eric D. Perfecto
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Patent number: 8645875Abstract: A method and system for quantifying manufacturing complexity of electrical designs randomly places simulated defects on image data representing electrical wiring design. The number of distinct features in the image data without the simulated defects and the number of distinct features in the image data with the simulated defects are determined and the differences between the two obtained. The difference number is used as an indication of shorting potential or probability that shorts in the wiring may occur in the electrical wiring design. The simulating of the defects in the image data may be repeated and the difference value from each simulation or run may be used to obtain a statistical average or representative shorting potential or probability for the design.Type: GrantFiled: October 28, 2010Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: Michael S. Cranmer, Richard P. Surprenant
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Publication number: 20110038525Abstract: A method and system for quantifying manufacturing complexity of electrical designs randomly places simulated defects on image data representing electrical wiring design. The number of distinct features in the image data without the simulated defects and the number of distinct features in the image data with the simulated defects are determined and the differences between the two obtained. The difference number is used as an indication of shorting potential or probability that shorts in the wiring may occur in the electrical wiring design. The simulating of the defects in the image data may be repeated and the difference value from each simulation or run may be used to obtain a statistical average or representative shorting potential or probability for the design.Type: ApplicationFiled: October 28, 2010Publication date: February 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael S. Cranmer, Richard P. Surprenant
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Patent number: 7873936Abstract: A method and system for quantifying manufacturing complexity of electrical designs randomly places simulated defects on image data representing electrical wiring design. The number of distinct features in the image data without the simulated defects and the number of distinct features in the image data with the simulated defects are determined and the differences between the two obtained. The difference number is used as an indication of shorting potential or probability that shorts in the wiring may occur in the electrical wiring design. The simulating of the defects in the image data may be repeated and the difference value from each simulation or run may be used to obtain a statistical average or representative shorting potential or probability for the design.Type: GrantFiled: January 4, 2008Date of Patent: January 18, 2011Assignee: International Business Machines CorporationInventors: Michael S. Cranmer, Richard P. Surprenant
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Publication number: 20090178016Abstract: A method and system for quantifying manufacturing complexity of electrical designs randomly places simulated defects on image data representing electrical wiring design. The number of distinct features in the image data without the simulated defects and the number of distinct features in the image data with the simulated defects are determined and the differences between the two obtained. The difference number is used as an indication of shorting potential or probability that shorts in the wiring may occur in the electrical wiring design. The simulating of the defects in the image data may be repeated and the difference value from each simulation or run may be used to obtain a statistical average or representative shorting potential or probability for the design.Type: ApplicationFiled: January 4, 2008Publication date: July 9, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael S. Cranmer, Richard P. Surprenant
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Patent number: 7325213Abstract: A structure for a system of chip packages includes a master substrate and at least one subset substrate of the master substrate. The subset substrate includes a portion of the master substrate that has an identical pin out pattern as the portion of the master substrate. The subset substrate has identical internal net lists as the portion of the master substrate. The subset substrate is adapted to accommodate a smaller chip than the master substrate. The master substrate is the largest substrate in the system. The invention also prepares a system of chip packages. The invention selects a master substrate and then selects a subset substrate of the master substrate.Type: GrantFiled: June 17, 2005Date of Patent: January 29, 2008Assignee: International Business Machines CorporationInventors: Harsaran S. Bhatia, Marie S. Cole, Michael S. Cranmer, Jason Lee Frankel, Eric Kline, Kenneth A. Papae, Paul R. Walling
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Patent number: 7088000Abstract: An integrated circuit structure and a method of manufacturing, wherein the method comprises forming a first via in an interconnect layer of the substrate, wherein the first via comprises a first size diameter; and forming a second via in the interconnect layer, wherein the second via comprises a second size diameter, the second size diameter being dimensioned larger than the first size diameter, wherein the second via comprises a non-uniform circumference, and wherein the substrate is configured in an approximately 1:1 ratio (i.e., approximately equal number) of the first and second vias. The first and second vias are laser formed or are formed by any of mechanical punching and photolithography. The second via is formed by sequentially forming multiple partially overlapping vias dimensioned and configured with the first size diameter. The first and second vias are arranged in a grid to allow for wiring of electronic devices.Type: GrantFiled: November 10, 2004Date of Patent: August 8, 2006Assignee: International Business Machines CorporationInventors: Michael S. Cranmer, Michael J. Domitrovits, Benjamin V. Fasano, Harvey C. Hamel, Charles T. Ryan
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Patent number: 6676784Abstract: A process for the manufacture of a multilayer ceramic substrate includes fabricating the multilayer ceramic substrate from a monolith fabricated from universal layers and a monolith fabricated from custom layers. The universal layer monolith and the custom layer monolith are then joined to form the complete structure of the MLC substrate.Type: GrantFiled: July 17, 2001Date of Patent: January 13, 2004Assignee: International Business Machines CorporationInventors: Christopher D. Setzer, Harsaran S. Bahatia, Raymond M. Bryant, Michael S. Cranmer, Suresh Kadakia, Richard O. Seeger, Satyapal Singh Bhatia
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Publication number: 20030015277Abstract: A process for the manufacture of a multilayer ceramic substrate includes fabricating the multilayer ceramic substrate from a monolith fabricated from universal layers and a monolith fabricated from custom layers. The universal layer monolith and the custom layer monolith are then joined to form the complete structure of the MLC substrate.Type: ApplicationFiled: July 17, 2001Publication date: January 23, 2003Applicant: International Business Machines CorporationInventors: Christopher D. Setzer, Harsaran S. Bahatia, Raymond M. Bryant, Michael S. Cranmer, Suresh Kadakia, Richard O. Seeger, Satyapal Singh Bhatia