Abstract: A method for transmitting and processing by a system packetized data stream comprising audio and video components and program guide information. The program guide information has a predetermined service identifier and includes service identifier information associated with audio and video program components. The program guide information is used to identify service identifiers associated with a selected program. The identified service identifiers are used to acquire data packets associated with the selected program. The acquired data packets are processed in accordance with a video signal standard to generate output signals representative of the selected program.

Abstract: A method and an apparatus for processing a packetized transport stream that determines whether a sequence of transport packets are received in a proper sequence and whether an error is present in a particular transport packet. The method includes the steps of determining a packet identifier for identifying transport packets associated with a selected program and parsing a packetized transport stream to identify and capture the desired sequence of transport packets in response to the packet identifier. The method further includes the steps of detecting a counter portion, determining whether a desired sequence of transport packets has been received in response to the counter portion, detecting a one bit toggle portion, and determining whether an error exits in the associated transport packet in response to the one bit toggle portion. An apparatus for implementing the method is also disclosed.

Abstract: A method and an apparatus for processing packetized signal having a plurality of channels carrying program information. The packetized signal also includes program guide information that includes channel identifier data. The program guide information comprises a sequence of data blocks including a segment map that includes information about the partitioning of the plurality of channels into segments and map block that includes information relating specific channels of the plurality of channels with respective channel identifier data.

Abstract: An access control system for signal processing applications includes an integrated circuit (IC) card, or “smart” card, that provides both security control and data descrambling functions. A security control processor in the smart card IC performs functions such as entitlement management and key generation. The smart card IC also includes a descrambler for processing data, such as video data, at high data rates. Mechanical characteristics of the smart card satisfy the ISO standard 7816-1. In addition, the interface to the smart card is via eight-terminals arranged on the surface of the card in accordance with ISO standard 7816-2. The eight terminal interface provides both high speed data I/O (input and output) required for data descrambling and ISO standard low speed serial data I/O.

Abstract: Apparatus in a receiver, for processing transmitted entitlement control information, includes a packet transport processor for selecting signal packets having payloads containing a conditional access payload header and a remaining payload of entitlement data. Respective payload headers include groups of bytes which are coded in a manner to allow or disallow the respective receiver from processing the entitlement data. A conditional access filter preprogrammed with a subscriber specific conditional access codeword examines respective byte groupings of the conditional access header for a match with the subscriber specific conditional access codeword. Only if a match occurs is the processor permitted to process the entitlement data. The entitlement data is thereafter utilized to generate decryption keys for descrambling portions of the transmitted signal.

Abstract: Apparatus and method for acquiring a program from a packetized signal in response to ancillary information included in the packetized signal. The packetized signal includes a plurality of program signals and ancillary information associated with the plurality of program signals. The apparatus includes means for identifying the ancillary information from the packetized signal, the ancillary information including master guide information for use in identifying and acquiring special guide information, and special guide information for use in acquiring program information associated with the plurality of program signals. The program signals may be acquired using identifier information that may be derived from the ancillary information. The apparatus includes means responsive to the ancillary information for acquiring a selected program from the packetized signal.

Abstract: Apparatus in a receiver, for processing transmitted entitlement control information, includes a packet transport processor for selecting signal packets having payloads containing a conditional access payload header and a remaining payload of entitlement data. Respective payload headers include groups of bytes which are coded in a manner to allow or disallow the respective receiver from processing the entitlement data. A conditional access filter preprogrammed with a subscriber specific conditional access codeword examines respective byte groupings of the conditional access header for a match with the subscriber specific conditional access codeword. Only if a match occurs is the processor permitted to process the entitlement data. The entitlement data is thereafter utilized to generate decryption keys for descrambling portions of the transmitted signal.

Abstract: In an inverse transport processor, program component packet payloads of respective program components are multiplexed to a memory data input port and directed to mutually exclusive areas of random access memory (RAM). The processor includes multiple direct memory access circuitry for writing the payloads of component data to the mutually exclusive blocks of the memory. Memory access for read and write functions are arbitrated so that no incoming program data can be lost, and all component processors are serviced.

Abstract: A system for interconnecting audio, video and data signals available in compressed form includes a bus having a plurality of channels for transmitting signal. A bus interface is located at respective signal processing devices, which interface includes a decoder to control the respective interface responsive to control signal transmitted in one of the channels. Data is transmitted in the channels in a superpacket structure. Processing devices which generate signal to be applied to the bus, such as a receiver which provides MPEG transport packets, include apparatus to form such superpackets. Respective superpackets include at least a transport packet and a timestamp related to the timing of occurrence of the transport packet. The transport packet and timestamp are located in predetermined positions within respective superpackets.

Abstract: An inverse transport processor system for a TDM packet signal TV receiver includes apparatus for selectively extracting desired payloads of program component data and coupling this data to a common buffer memory data input port. A microprocessor associated with the system also couples data to the common buffer memory data input port. The respective component payloads and data generated by the microprocessor are stored in respective blocks of the common buffer memory in response to associated memory address which are applied to a memory address input port by an address multiplexer. A decryption device is included to decrypt payload data according to packet specific decryption keys. In addition a detector is included to detect payloads including entitlement data. Payloads containing entitlement data are directed via the common buffer memory to a smart card which generates the packet specific decryption keys.

Abstract: In an inverse transport processor, program component packet payloads of respective program components are directed to select areas of random access memory (RAM) (18) in accordance with a plurality of start and end pointers which are stored in a first plurality (86, 89) of registers, one for each program component. Addresses are generated, in part, by a plurality of read pointer registers (82) multiplexed with an adder (80) to successively increment the pointers for respective program components. The start pointers are associated with read pointers to from memory addresses that scroll through designated memory blocks selectively assigned to respective program components. Memory access for read and write functions are arbitrated (98) so that no incoming program data can be lost, and all component processors are serviced.

Abstract: In an inverse transport processor of the type which directs video payloads of a packet signal to buffer memory space, apparatus is included for writing a media error codes at sequential first memory address locations in the memory ahead of each packet payload. Concurrently a processor examines the current packet to determine if it occurs in proper sequence. If a packet is lost, the payload is written to memory in subsequent sequential address locations. If there is no packet loss, the sequential first memory address locations are simply overwritten by the packet payload to excise the undesired media error code. Media error codes can thus be inserted in the packet payload stream without creating timing obstacles, for a system designer.

Abstract: Apparatus for selecting predetermined ones of packets of signal components, from a signal stream of packets includes a control device, responsive to user selection and a transmitted program guide, for determining packet identifier codes, SCID's, for respective program signal components. The respective component SCID's are stored in progrommable registers. SCID's, from respective packets in the signal stream, are successively loaded into a further register. Comparators which are associated with the programmable registers, compare the stored SCID's with the SCID's from packets in the signal stream. Output signals from the respective comparators control the utilization of the respective signal component packets in the signal stream. Programming of SCID's in the respective programmable registers is performed according to a schedule to preclude undesired data inadvertently being accepted by the system.

Abstract: A receiver (FIG. 2 ) for decoding associated compressed video and audio information components transmitted in mutually exclusive "frames" of data with respective time stamps PTS.sub.vid and PTS.sub.aud respectively, includes a controller (216) which is responsive to the respective received time stamps to provide coarse synchronization by delaying or skipping respective frames of one or the other of the components to approximately time align the two components. Fine synchronization is provided by adjusting the processing or clock frequency (215) of the audio signal processor (212) independent of the video processor (214). The control for the frequency adjustment is related to the difference between audio and video time stamps.

Abstract: Apparatus for developing synchronization of an intermediate layer of signal such as the transport or multiplex layer of a multi-layered compressed video signal, includes at the encoding end of the system a modulo K counter which is clocked responsive to a system clock, and the count valued is embedded in the signal at the transport layer according to a predetermined schedule. At the receiving end of the system a similar counter is responsive to a controlled receiver clock signal and the count value of this counter is sampled at the arrival of the count values embedded in the transport layer. The differences of successive sampled count values of the receiver counter are compared with the differences of corresponding successive values of the embedded count values in the transport layer to provide a signal to control the receiver clock signal.

Abstract: The digitized video image data stored in a video RAM in a pix-in-pix television receiver is modified by the addition of digital data from an external computer via a computer interface circuit under control of the pix-in-pix controller. The computer interface circuit is coupled to the internal controller of the television receiver via an external input terminal. The additional digital data received from the external computer may be representative of either text or graphics to be merged into the stored video image.

Abstract: The stored digitized video image data stored in a video RAM is transferred from the video RAM in a pix-in-pix television receiver to an external computer via a computer interface circuit under control of the pix-in-pix controller. The computer interface circuit is coupled to the internal controller of the television receiver via an external terminal. The external terminal receives digital control data from the external computer and conveys the stored digitized video image data signals from the video RAM to the external computer.

Abstract: A video component interconnection system includes a single signal conductor video bus serially coupled between each of the video components for conducting video signal between the components. A switch located in series with the video bus separates the continuity of the video bus when it is non-conductive. A shunt switch arrangement coupled to the video bus at its junction with the series switch, applies an impedance substantially equal to the characteristic impedance of the video bus between the video bus and a reference potential, when the series switch separates the continuity of the video bus, in order to reduce ghost-producing reflections.

Abstract: A signal switching arrangement includes first and second switches coupled between a signal input terminal and a signal output terminal. A bias signal for causing the first switch to couple an input signal to the second switch is applied to the output terminal. The second switch is controlled by a control signal to selectively couple the bias signal to the first switch, thereby causing the input signal to be coupled to the output terminal through both switches. The arrangement is particularly well suited to form a relatively inexpensive signal multiplexer with good isolation characteristics.

Abstract: A video component interconnection system includes a single signal conductor video bus serially coupled between each of the video components for conducting video signal between the components. A switch located in series with the video bus separates the continuity of the video bus when it is non-conductive. A shunt switch arrangement coupled to the video bus at its junction with the series switch, applies an impedance substantially equal to the characteristic impedance of the video bus between the video bus and a reference potential, when the series switch separates the continuity of the video bus, in order to reduce ghost-producing reflections.