Abstract: A test and measurement instrument including a plurality of channels, each channel configured to receive a corresponding input signal. Each channel includes a comparator configured to compare the input signal to a threshold for the channel; an edge detector configured to detect an edge of an output signal of the comparator; and a threshold controller configured to adjust the threshold for the channel in response to the edge detector.

Abstract: A test and measurement instrument including a port including a plurality of connections; an impedance sense circuit configured to sense an impedance coupled to a connection of the plurality of connections; and a controller configured to setup the test and measurement instrument in response to a sensed impedance from the impedance sense circuit.

Abstract: A test and measurement instrument including a plurality of channels, each channel configured to receive a corresponding input signal. Each channel includes a comparator configured to compare the input signal to a threshold for the channel; an edge detector configured to detect an edge of an output signal of the comparator; and a threshold controller configured to adjust the threshold for the channel in response to the edge detector.

Abstract: A test and measurement instrument including a port including a plurality of connections; an impedance sense circuit configured to sense an impedance coupled to a connection of the plurality of connections; and a controller configured to setup the test and measurement instrument in response to a sensed impedance from the impedance sense circuit.

Abstract: A method of trace delay error compensation for measurements that are taken remotely from the signal source or receiver of a circuit uses data available from a computer aided design (CAD) tool to characterize electrical connections to an instrument measurement point, such as a connectorless probe, which is remote from the signal source or receiver. Extracted parameters from the CAD data are applied to signals acquired by the probe to adjust the signal timing and/or shape to more accurately represent the signal information timing at the signal source or receiver or other remote location of interest to a user. The corrected signals at the desired location may be displayed by a measurement instrument.

Abstract: A logic analyzer having clock channels and data channels includes digitizer followed by a digital filter in each channel, the digital filter compensating for losses in signal fidelity in a signal under test. The resulting enhanced multi-bit samples are stored in respective waveform memories for subsequent display as analog waveforms and as logic data. The multi-bit samples from each channel are re-sampled by a regenerated sample clock to determine the logic values of the signal at precise times. For high speed serial data, each channel is divided into multiple clock channels and sampling channels, the outputs from the clock channels being phase adjusted to provide a precise sample clock to the sampling channels and the outputs from the sampling channels being combined to form a serial data output.

Abstract: A logic analyzer having clock channels and data channels includes digitizer followed by a digital filter in each channel, the digital filter compensating for losses in signal fidelity in a signal under test. The resulting enhanced multi-bit samples are stored in respective waveform memories for subsequent display as analog waveforms and as logic data. The multi-bit samples from each channel are re-sampled by a regenerated sample clock to determine the logic values of the signal at precise times. For high speed serial data, each channel is divided into multiple clock channels and sampling channels, the outputs from the clock channels being phase adjusted to provide a precise sample clock to the sampling channels and the outputs from the sampling channels being combined to form a serial data output.

Abstract: A plurality of digital samplers operating on a common signal under test (SUT) sample the SUT at a sample rate beyond that which guarantees monotonic sampling and non-overlapping setup and hold windows for adjacent samplers. Subsequent processing of the sample streams restores monotonicity and sample independence to provide thereby a very high effective sample rate.

Abstract: A method and apparatus for synchronizing presentation of multi-domain measurements using actual or quasi 3-D representation. The synchronization between data streams acquired in different measurement domains is performed by using timestamps, a common trigger event, or a common clock, or a combination of any or all of them. In this way, for example, a transient anomaly in the RF spectrum of a communications signal may be correlated with, and displayed with, a related corrupted data communications packet.

Abstract: A data transformation algorithm is selectively applied to each data vector as it enters the pipelined structure. In a selection step, the algorithm compares the bit value of the new data vector with the corresponding bit values of the preceding data vector, and sums the number of logic transitions. The transformation algorithm is applied to the new data vector only if it would reduce the resulting number of transitions, otherwise the data vector is propagated unmodified. Bit inversion is a data transformation algorithm according to the present invention that provides up to a 50% reduction in the number of logic transitions.

Abstract: A plurality of digital samplers operating on a common signal under test (SUT) sample the SUT at a sample rate beyond that which guarantees monotonic sampling and non-overlapping setup and hold windows for adjacent samplers. Subsequent processing of the sample streams restores monotonicity and sample independence to provide thereby a very high effective sample rate.

Abstract: An expanded WIRE-OR Bus structure has a first WIRE-OR Bus arrangement and a second WIRE-OR Bus arrangement. Each of the first and second WIRE-OR Bus arrangements have connected thereto at least one driver element and at least one receiver element. An intelligent bi-directional signal coupling circuit includes a buffer element, a bus arbiter, and a bus driver amplifier. The coupling circuit couples signals between the first WIRE-OR bus and the WIRE-OR second bus, and prevents signals originating on one of the WIRE-OR buses from being coupled back to the same WIRE-OR bus.

Abstract: Apparatus for data bus expansion between two instrument chassis comprises a first interface circuit, a connecting cable, and a second interface circuit. Detection circuitry in each interface circuit detects slot position. Slot position determines direction of address and data flow for each card. One of the first and second interface circuits is connected to a controller slot in a first chassis, and the other of the first and second interface circuits is connected to a non-controller slot in a second chassis. Bus interface circuitry for signal and identification are reconfigured in accordance with slot determination. As a result, the assembly formed by connection of two substantially identical interface cards with a cable, is symmetric and reversible.

Abstract: Apparatus for monitoring a signal at an intermediate point on a series impedance source terminated unidirectional transmission line employs a voltage probe, a current probe, and a summing element. The apparatus provides a useful output signal despite the fact that signals at an intermediate point on the transmission line comprise the sum of incident and reflected waveforms. The voltage probe derives a signal from the transmission line that is representative of the sum of the incident and reflected waveforms. The current probe produces a voltage signal representative of the difference between the incident and reflected waveform currents. The summing circuit algebraically adds the output signals of the voltage and current probes, and produces an output signal representative of only one of the transmitted waveform or the reflected waveform.

Abstract: A data transformation algorithm is selectively applied to each data vector as it enters the pipelined structure. In a selection step, the algorithm compares the bit value of the new data vector with the corresponding bit values of the preceding data vector, and sums the number of logic transitions. The transformation algorithm is applied to the new data vector only if it would reduce the resulting number of transitions, otherwise the data vector is propagated unmodified. Bit inversion is a data transformation algorithm according to the present invention that provides up to a 50% reduction in the number of logic transitions.

Abstract: A multiple digital event generator produces events with timing that is programmable, yet the event generator requires a minimum of circuitry for its construction and is capable of operating at very high speeds. A linear feedback shift register is used to produce an arbitrary sequence of non-repeating binary numbers. These numbers are then monitored by one or more digital comparators whose other digital input is chosen so as to cause the desired event to occur when a certain number in the number sequence occurs. The minimum time between events and the maximum range of event control timing is adjustable by varying the frequency of the clock input to the linear feedback shift register. Maximum speed is achieved by using one set of the shift register flip-flop outputs (Q or Q-not) for internal feedback and the other set (Q-not or Q) for the output to the digital comparators, so that the speed of operation of the shift register is not degraded by the load of the multiple digital comparator circuits on its output.

Abstract: An input apparatus for a multi-channel device, such as a logic analyzer, is disclosed, the input apparatus providing the multi-channel device with a programmable set-up and hold feature. The multi-channel device acquires a logic signal from a product under test, the logic signal having associated therewith an actual set-up and hold time with respect to an external clock signal. The actual set-up and hold times are entered into the multi-channel device via a keyboard and a display. The device has stored therein a desired set-up and hold time required by the logic signal relative to the external clock signal. In accordance with the actual and the desired set-up and hold times, the multi-channel device changes the relative orientation of the acquired logic signal with respect to the external clock signal, along the time axis until the set-up and hold times of the acquired logic signal are changed from the actual value to the desired value.