Abstract: Power management techniques for external cache memories of computers are disclosed. The power management techniques operate to reduce power consumption of an external cache memory of a computer system by intelligently placing the external cache memory in a low power mode. In one embodiment of the invention, a computer operates using event loop and an idle loop. The computer generally remains in the event loop while there is activity that requires processing, but enters the idle loop when there is no activity so that power consumption is lowered. The power management techniques according to the invention reduce power consumption of the computer by placing the external cache memory in the low power state upon entering the idle loop, and then awakening the external cache memory as the microprocessor awakens or upon exiting the idle loop. The power savings provided by the invention are particularly suitable for use with battery powered computing devices.