Patents by Inventor Michael S. Hicken

Michael S. Hicken has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8806112
    Abstract: A method for handling meta data stored in a page of a flash memory within a flash media controller. The method generally includes (i) defining the meta data on a per context basis, where the context is defined on a per page basis, (ii) when a size of the meta data is less than or equal to a predefined threshold, storing the complete meta data within a structure of the context, and (iii) when the size of the meta data is greater than the predefined threshold, defining meta data pointers within the context.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: August 12, 2014
    Assignee: LSI Corporation
    Inventors: Vinay Ashok Somanache, Michael S. Hicken, Pamela S. Hempstead, Timothy W. Swatosh, Jackson L. Ellis, Martin S. Dell
  • Patent number: 8645618
    Abstract: A method of controlling a flash media system. The method includes providing a flash lane controller having a processor control mode and creating and presenting soft contexts. The soft contexts generally place the flash lane controller into the processor control mode. In the processor control mode, the flash lane controller stores the entire soft context, finishes executing any outstanding contexts, suspends normal hardware automation, and then executes the soft context.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: February 4, 2014
    Assignee: LSI Corporation
    Inventors: Vinay Ashok Somanache, Jackson L. Ellis, Michael S. Hicken, Timothy W. Swatosh, Martin S. Dell, Pamela S. Hempstead
  • Publication number: 20130019053
    Abstract: A flash media controller including one or more dedicated data transfer paths, one or more flash lane controllers, and one or more flash bus controllers. The one or more flash lane controllers are generally coupled to the one or more dedicated data transfer paths. The one or more flash bus controllers are generally coupled to the one or more flash lane controllers.
    Type: Application
    Filed: March 28, 2012
    Publication date: January 17, 2013
    Inventors: Vinay Ashok Somanache, Timothy W. Swatosh, Pamela S. Hempstead, Jackson L. Ellis, Michael S. Hicken, Martin S. Dell
  • Publication number: 20130019050
    Abstract: A method of controlling a flash media system. The method includes providing a flash lane controller having a processor control mode and creating and presenting soft contexts. The soft contexts generally place the flash lane controller into the processor control mode. In the processor control mode, the flash lane controller stores the entire soft context, finishes executing any outstanding contexts, suspends normal hardware automation, and then executes the soft context.
    Type: Application
    Filed: December 21, 2011
    Publication date: January 17, 2013
    Inventors: Vinay Ashok Somanache, Jackson L. Ellis, Michael S. Hicken, Timothy W. Swatosh, Martin S. Dell, Pamela S. Hempstead
  • Publication number: 20130019051
    Abstract: A method for handling meta data stored in a page of a flash memory within a flash media controller. The method generally includes (i) defining the meta data on a per context basis, where the context is defined on a per page basis, (ii) when a size of the meta data is less than or equal to a predefined threshold, storing the complete meta data within a structure of the context, and (iii) when the size of the meta data is greater than the predefined threshold, defining meta data pointers within the context.
    Type: Application
    Filed: December 22, 2011
    Publication date: January 17, 2013
    Inventors: Vinay Ashok Somanache, Michael S. Hicken, Pamela S. Hempstead, Timothy W. Swatosh, Jackson L. Ellis, Martin S. Dell
  • Publication number: 20130019052
    Abstract: An apparatus including a first circuit, a second circuit, and a third circuit. The first circuit may be configured to maintain die-based information used for operation of a flash lane controller (FLC). The second circuit may be configured to manage contexts that are actively being processed by the flash lane controller (FLC). The third circuit may be configured to perform pipeline execution of a plurality of the contexts managed by the second circuit.
    Type: Application
    Filed: January 5, 2012
    Publication date: January 17, 2013
    Inventors: Vinay Ashok Somanache, Jackson L. Ellis, Pamela S. Hempstead, Timothy W. Swatosh, Michael S. Hicken, Martin S. Dell
  • Publication number: 20100287320
    Abstract: Described embodiments provide interprocessor communication between at least two processors of an integrated circuit, each processor running at least one task. For each processor, a proxy task is generated corresponding to each task running on each other processor. A task identifier for each task, and a look-up table having each task identifier associated with each other processor running the task is also generated. When a message is sent from a source task to a destination task that is running on a different processor than the source task, the source task communicates with the proxy task of the destination task. The proxy task appends the task identifier for the destination task to the message and sends the message to an interprocessor communication interface. Based on the task identifier, the processor running the destination task is determined and the destination task retrieves the message.
    Type: Application
    Filed: May 6, 2009
    Publication date: November 11, 2010
    Inventors: Carlos Querol, James N. Snead, Michael S. Hicken, Randal S. Rysavy, Carl E. Forhan
  • Patent number: 7293196
    Abstract: A method, apparatus, and system for preserving the cache data of redundant storage controllers, by copying the recorded data blocks and the associated cache tags in the primary cache memory of a storage controller to a secondary cache memory of an alternate, redundant storage controller, wherein upon a failure occurring in the primary cache memory of any of the storage controllers, subsequent storage requests from a host, previously intended for processing by the failed storage controller, are processed through the secondary cache memory of a non-failed, redundant storage controller that contains the failed storage's controller cache data and cache tags.
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: November 6, 2007
    Assignee: Xiotech Corporation
    Inventors: Michael S. Hicken, James N. Snead
  • Publication number: 20040153727
    Abstract: A method, and apparatus for recovering cache data of a failed redundant storage controller and reestablishing redundancy by mirroring cache data of a primary cache memory of a first storage controller in a secondary cache memory of another storage controller. Upon a failure occurring in a storage controller, the failure is detected and, in response, a structured list of cache tags is created in the controller where having the secondary cache that is the mirror of the primary cache of the failed controller.
    Type: Application
    Filed: May 5, 2003
    Publication date: August 5, 2004
    Inventors: Michael S. Hicken, Steven M. Howe, James N. Snead
  • Publication number: 20030212864
    Abstract: A method, apparatus, and system for preserving the cache data of redundant storage controllers, by copying the recorded data blocks and the associated cache tags in the primary cache memory of a storage controller to a secondary cache memory of an alternate, redundant storage controller, wherein upon a failure occurring in the primary cache memory of any of the storage controllers, subsequent storage requests from a host, previously intended for processing by the failed storage controller, are processed through the secondary cache memory of a non-failed, redundant storage controller that contains the failed storage's controller cache data and cache tags.
    Type: Application
    Filed: May 7, 2003
    Publication date: November 13, 2003
    Inventors: Michael S. Hicken, James N. Snead
  • Publication number: 20030212865
    Abstract: A method and apparatus for flushing a write cache includes receiving a read or a write storage request, determining whether the storage request comprises a full or partial hit with data stored in a write cache one or more lines, some of which may be dirty. If the hit is partial and the one or more lines of the data are dirty, flushing the dirty data. If the hit is full or partial and any of the write cache lines are not dirty, and the storage request is a write request, flushing the dirty write cache lines, invalidating the non dirty write cache line, writing the storage request data into the write cache as a new write cache line and marking the new write cache line dirty. If the hit is full, all write cache lines are marked dirty, and the storage request is a write request, overlaying the cache write line with the storage request data and marking the write cache line as dirty.
    Type: Application
    Filed: May 8, 2003
    Publication date: November 13, 2003
    Inventors: Michael S. Hicken, James N. Snead
  • Patent number: 5822142
    Abstract: A disk drive includes a disk having a plurality of tracks. The disk is formatted so that the tracks are grouped into zones. Each of the tracks within a zone on a particular surface of the disk is written with the same data rate. The disk is formatted with sectors having no sector ID fields. The disk also includes groupings of tracks called sparing partitions. Sparing partitions generally contain less tracks than the number of tracks within a zone. A desired number of spare sectors are placed in each sparing partition and some of the spare sectors are used at manufacture while at least one of the spare sectors in sparing partition is reserved for future use. The disk also includes spare tracks and the disk drive has the capability of identifying bad tracks or defects in the servo areas of a track which make it difficult for the transducer to track follow. Bad tracks are skipped and a spare track is used.
    Type: Grant
    Filed: July 26, 1996
    Date of Patent: October 13, 1998
    Assignee: Western Digital Corporation
    Inventor: Michael S. Hicken