Abstract: A method and structure is provided to test for leakage currents in a fuse array. A diode is connected to each column in the array in order to isolate the column from the test circuitry during normal operation of the device. During testing, current is fed through a diode to a column, and the corresponding leakage current is measured. In one embodiment, the anodes of each diode are connected in common to a single test point, and the total leakage current from the entire fuse array is measured simultaneously. In another embodiment, addressing means are used to selectively address a desired one of the test diodes and thus a corresponding one of the columns such that leakage current through a single column.

Abstract: The present invention provides circuitry for disabling the output gate of an ECL programmable array logic device so that TTL programming and test signals may be applied to the ECL output node. The disable control circuit is responsive to a control signal to provide pull down current to the ECL output gate. A sensing circuit connected to the ECL output senses the TTL voltage level on the output in the programming mode without disturbing the ECL output in the normal mode.

Abstract: The present invention provides circuitry for controlling the programming current provided to the fuse array of an ECL programmable array logic device. The control circuit includes an array driver connected to provide current to the row line, a current source connected to provide current to the array driver in response to an input signal, and a reference circuit which controls the current provided by the current source.

Abstract: A programmable read-only memory circuit including a plurality of fusible link memory cells is disclosed in which a first auxiliary current source is employed to selectively isolate a cell location to be volatized during memory personalization and a second auxiliary current source is employed to volatize or personalize a fusable link in the selected memory cell for insuring complete volatilization of the fusible link.

Abstract: A bipolar sense-write circuit is provided for sensing voltage levels representative of a logical "1" or a logical "0" stored in a flip-flop storage cell and for writing voltage levels into the flip-flop storage cell. The sense portion of the sense-write circuit is essentially independent of the write portion thereof. The sense circuitry portion of the sense-write circuit includes circuitry for biasing a pair of bit lines at substantially equal voltages at all times, except during a write cycle, to a voltage which facilitates sensing of a selected storage cell and which also results in the write circuitry being essentially electrically isolated from the sense-bit lines during a read cycle. During a write cycle, the read circuitry is effectively disabled so that the bit lines are at voltages determined by the write circuitry, and the read circuitry is effectively isolated from the sense-bit lines during the write cycle, and the write circuitry applies an increased voltage to one of the sense-bit conductors.

Abstract: An N-bit binary address decoder suitable for use in an emitter-coupled logic bipolar random access memory (RAM) is provided. Each of the N address input signals is applied to an input terminal and is level shifted and applied to the input node of an emitter-coupled logic inverter. The outputs of the emitter-coupled logic inverter are the collectors of the emitter-coupled transistors on which complementary output signals representative of the corresponding binary address input signal are produced. The complementary output signals generated by the N inverters are connected to 2.sup.N AND gates to form the possible 2.sup.N minterm combinations. Each of the AND gates includes a load resistor coupled to a power supply and N Schottky diodes having their anodes coupled to the load resistor and their cathodes coupled to the corresponding address inverter output terminals.

Abstract: A bipolar sense-write circuit is provided for sensing voltage levels representative of a logical "1" or "0" stored in a flip-flop storage cell and for writing voltage levels into the flip-flop storage cell. The sense-write circuit includes first and second amplifier stages which, when coupled to a selected flip-flop storage cell produce a voltage in the amplifier section approximately equal to the voltage on a collector node in the flip-flop storage cell. Each amplifier stage of the sense-write circuit utilizes a side of the selected flip-flop storage cell as a part of that amplifier stage, if the corresponding side of the flip-flop storage cell is "on". The amplifier stage connected to the "on" side of the selected flip-flop storage cell acts as a unity gain amplifier, such that the row selection voltage appears at the output of that amplifier stage.