Abstract: A test and measurement instrument, including one or more ports configured to receive a stream of packets from a transmitter through a network component, each packet including a timestamp; and one or more processors. The one or more processors are configured to select a buffer model, the buffer model including one or more validation thresholds for a buffer fullness, determine a network delay based on the timestamp in each packet and when the packet was received at the one or more ports, and compensate the buffer model based on the network delay to determine a buffer fullness value based on the stream of packets. The test and measurement instrument also includes a display to display an indication of whether the transmitter complies with the selected buffer model, so a user can confirm whether a transmitter being tested complies with applicable standards.

Abstract: A network oscilloscope, including a network interface configured to receive a stream of network data, one or more processors, and a display. The one or more processors generate a timestamp for each data packet parsed from the stream of network data, extract a portion of information from each of the data packets received from the stream of network data, the portion of information being less than an entirety of information in each data packet, and generate a data record indicating extracted information and a timestamp for each data packet parsed from the stream of network data. The display configured to display at least a portion of the data record.

Abstract: Embodiments of the invention are directed to a system for generating video test pattern signals from definitions contained in a text-based definition file. The definition file allows the user to create generic definitions for test signals that can be interpreted to create test signals in a variety of formats, raster sizes, color spaces, sample structures, frame modes, and bit depths. A parametric generator uses one or more engines to then generate the desired test pattern from the definition file.

Abstract: Embodiments of the invention include a test and measurement device, system, and method for synchronizing measurement views and configuration parameters across multiple input channels or devices. A method includes receiving signals under test associated with multiple input channels of the test and measurement instrument or with multiple devices, selecting a measurement view of one input signal or device, receiving a synchronized view enable preference from a user control interface, and synchronizing the measurement view or configuration parameters of the other signals or devices with what was chosen on the first signal or device. A test and measurement instrument includes input terminals to receive the input signals, a user control interface to receive input from an operator, a display to provide measurement information about the input signals, and a synchronization control unit to synchronize measurement views and/or configuration parameters between the inputs or devices.

Abstract: Embodiments of the invention include a network-based timing instrument that has a master unit and an internal switch that communicate with a slave device. The master unit includes a timing compensator. The internal switch is coupled to the master unit by the internal network and is also coupled to an external network that is outside of the network-based timing instrument. The internal switch is structured to provide speed information of the internal network and the external network to the master unit, and the timing compensator of the master unit is modified based on the speed information provided by the internal switch. The master unit may also modify the timing compensator based on a message length of messages sent by the master unit. Also the internal switch may be structured to provide incoming and/or outgoing message residence time information to the master unit, and the master unit may modify the timing compensator based on such residence time information.

Abstract: A relay fault detection and correction system includes a signal detector structured to measure primary and secondary signals, and generates a fault output signal if the signals appear to be unterminated due to a relay not connecting the signals to the loads. A cycle circuit is structured to cause a relay controller to cycle a potentially under-performing relay between its states a number of times after the signal detector generates the fault output.

Abstract: A stochastic system in a waveform monitor reduces the amount of memory used to store waveform data as it is being accumulated. The system produces a high quality trace display using fewer bits of memory by incrementing pixels using stochastic methods. In at least some embodiments, possible memory values are divided into two or more value ranges and an increment percentage is ascribed for each of the value ranges. During operation, first a present stored value is read from the memory store and its ascribed increment percentage for the particular range is selected. Then the present stored value is stochastically incremented based on the percentage for the particular range.

Abstract: A relay fault detection and correction system includes a signal detector structured to measure primary and secondary signals, and generates a fault output signal if the signals appear to be unterminated due to a relay not connecting the signals to the loads. A cycle circuit is structured to cause a relay controller to cycle a potentially under-performing relay between its states a number of times after the signal detector generates the fault output.

Abstract: A video timing display for multi-rate systems allows a user to quickly, easily and precisely measure the timing difference between video signals of different rates. A graphic display area within a raster display region provides a display of vertical and horizontal timing offsets of one video signal with respect to another video signal as a reference having a different frame rate. The graphic display area includes a reference indicator associated with the reference and timing indicators indicating the timing phases between the video signals, with one of the timing indicators being emphasized. A numeric display area may be provided adjacent the graphic display area to display the actual vertical and horizontal timing differences in appropriate units for the emphasized timing indicator relative to the reference indicator with a precision to one video clock cycle.

Abstract: A flexible timebase for eye diagrams uses a stable free running oscillator as a sample clock for equivalent time sampling of an input serial digital signal and of a reference signal, derived from a subdivided recovered clock of the input serial digital signal. The reference signal samples are provided to a digital phase-locked loop that provides the flexible timebase to an eye pattern generator. The eye pattern generator accumulates the input serial digital signal samples at times corresponding to the reference signal samples to produce the eye diagram. A linear phase detector in the digital phase locked loop converts the reference signal samples to a complex signal using a Hilbert transform and then to a linear ramp of phase values using a CORDIC algorithm with arctangent lookup table. A subtractor then subtracts the digital phase-locked loop feedback from the linear ramp to provide the input to the loop filter.

Abstract: A flexible timebase for eye diagrams uses a stable free running oscillator as a sample clock for equivalent time sampling of an input serial digital signal and of a reference signal derived from a subdivided recovered clock of the input serial digital signal. The reference signal samples are provided to a digital phase-locked loop that provides the flexible timebase to an eye pattern generator. The eye pattern generator accumulates the input serial digital signal samples at times corresponding to the reference signal samples to produce the eye diagram. A linear phase detector in the digital phase locked loop converts the reference signal samples to a complex signal using a Hilbert transform and then to a linear ramp of phase values using a CORDIC algorithm with arctangent lookup table. The digital phase-locked loop feedback is subtracted from the linear ramp to provide the input to the loop filter.

Abstract: Embodiments of the invention are directed to a system for generating video test pattern signals from definitions contained in a text-based definition file. The definition file allows the user to create generic definitions for test signals that can be interpreted to create test signals in a variety of formats, raster sizes, color spaces, sample structures, frame modes, and bit depths. A parametric generator uses one or more engines to then generate the desired test pattern from the definition file.

Abstract: A flexible timebase for eye diagrams uses a stable free running oscillator as a sample clock for equivalent time sampling of an input serial digital signal and of a reference signal, such as a sine wave, derived from a subdivided recovered clock of the input serial digital signal. The reference signal samples are provided to a digital phase-locked loop that provides the flexible timebase to an eye pattern generator. The eye pattern generator accumulates the input serial digital signal samples at times corresponding to the reference signal samples to produce the eye diagram. A linear phase detector in the digital phase locked loop converts the reference signal samples to a complex signal using a Hilbert transform and then to a linear ramp of phase values using a CORDIC algorithm with arctangent lookup table. A subtractor is then used to subtract the digital phase-locked loop feedback from the linear ramp to provide the input to the loop filter.

Abstract: Embodiments of the invention include a test and measurement device, system, and method for synchronizing measurement views and configuration parameters across multiple input channels or devices. A method includes receiving signals under test associated with multiple input channels of the test and measurement instrument or with multiple devices, selecting a measurement view of one input signal or device, receiving a synchronized view enable preference from a user control interface, and synchronizing the measurement view or configuration parameters of the other signals or devices with what was chosen on the first signal or device. A test and measurement instrument includes input terminals to receive the input signals, a user control interface to receive input from an operator, a display to provide measurement information about the input signals, and a synchronization control unit to synchronize measurement views and/or configuration parameters between the inputs or devices.

Abstract: Aspects of the present invention are related, in general, to Type-III phase-locked loops. In particular, aspects of the present invention relate to analog Type-III phase-locked loop arrangements comprising at least two signal paths, wherein each signal path may correspond to a bandwidth partition and may be selected by a selector according to a bandwidth parameter value. According to one aspect of the present invention, a first signal path may correspond to a fast loop (wide closed-loop bandwidth), and a second signal path may correspond to a slow loop (narrow closed-loop bandwidth).

Abstract: Aspects of the present invention are related, in general, to Type-III phase-locked loops. In particular, aspects of the present invention relate to analog Type-III phase-locked loop anangements comprising at least two signal paths, wherein each signal path may correspond to a bandwidth partition and may be selected by a selector according to a bandwidth parameter value. According to one aspect of the present invention, a first signal path may correspond to a fast loop (wide closed-loop bandwidth), and a second signal path may correspond to a slow loop (narrow closed-loop bandwidth).

Abstract: A luminance qualified vector display device provides a vector display that is gated by a specified luminance range. In one implementation three luminance gates may be used, one for luminance levels above a specified high luminance threshold, a second for luminance levels below a specified low luminance threshold, and a third for luminance levels between the specified high and low luminance thresholds. Also the luminance thresholds for the medium luminance range may be separately adjusted to overlap the high and low luminance ranges respectively. Each luminance qualified vector display may be displayed separately, may be overlaid for display using a different color for each luminance range, or may be displayed in different quadrants of a display device or window together with the normal, non-luminance qualified, vector display.

Abstract: A two-dimensional video timing display with numeric readouts allows a user to quickly, easily and precisely measure the timing difference between video signals. A graphic display area within a raster display region provides a two-dimensional display of vertical timing offset and horizontal timing offset of an input video signal with respect to a reference video signal, the graphic display area including a reference indicator centered in the graphic area indicating the timing of the reference video signal and a timing indicator in the graphic area indicating the timing of the input video signal with respect to the reference video signal. A numeric display area is adjacent the graphic display area to display the actual vertical and horizontal timing offsets in appropriate units according to the format of the input video signal with a precision to one video clock cycle.

Abstract: A video timing display for multi-rate systems allows a user to quickly, easily and precisely measure the timing difference between video signals of different rates. A graphic display area within a raster display region provides a display of vertical and horizontal timing offsets of one video signal with respect to another video signal as a reference having a different frame rate. The graphic display area includes a reference indicator associated with the reference and timing indicators indicating the timing phases between the video signals, with one of the timing indicators being emphasized. A numeric display area may be provided adjacent the graphic display area to display the actual vertical and horizontal timing differences in appropriate units for the emphasized timing indicator relative to the reference indicator with a precision to one video clock cycle.

Abstract: A two-dimensional video timing display with numeric readouts allows a user to quickly, easily and precisely measure the timing difference between video signals. A graphic display area within a raster display region provides a two-dimensional display of vertical timing offset and horizontal timing offset of an input video signal with respect to a reference video signal, the graphic display area including a reference indicator centered in the graphic area indicating the timing of the reference video signal and a timing indicator in the graphic area indicating the timing of the input video signal with respect to the reference video signal. A numeric display area is adjacent the graphic display area to display the actual vertical and horizontal timing offsets in appropriate units according to the format of the input video signal with a precision to one video clock cycle.