Patents by Inventor Michael S. Quayle

Michael S. Quayle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10643012
    Abstract: Techniques and systems for concurrent formal verification of logic synthesis are described. A synthesis tool can write intermediate checkpoint designs that embody the state of an integrated circuit (IC) design under synthesis as optimization progresses. Meanwhile, formal equivalence checking proceeds in parallel with synthesis and checks the intermediate checkpoint designs for equivalence.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: May 5, 2020
    Assignee: Synopsys, Inc.
    Inventors: Lisa R. McIlwain, Michael S. Quayle, Eyal Odiz, Patrick Groeneveld, John W. Hagerman, Kshama Jambhekar, Phillip W. Baraona