Abstract: A computer system is provided including a central processing unit having an internal cache, a memory controller is coupled to the central processing unit, and a closely coupled peripheral is coupled to the central processing unit. A coherent interconnection may exist between the internal cache and both the memory controller and the closely coupled peripheral, wherein the coherent interconnection is a bus.

Abstract: A virtual network interface system with memory management is provided, including a network interface controller having a memory with a memory credit and a flow-control for managing the network interface controller. A computer cluster is linked to the network interface controller for exchanging the memory credit with the network interface controller.

Abstract: The present disclosure includes a system and method for managing network and server power. In an example of managing network and server power according to the present disclosure, routing network traffic is routed onto a number of core networks based on core network statistics, capacity requirements are determined based on core network statistics for the number of core networks and for a number of servers operating a number of virtual machines on the number of core networks, wherein the number of core networks include a number of core switches and a number of edge switches, and the capacity is set for the number of core switches based on the capacity requirements for the number of core networks and for the number of servers based on the capacity requirements for the number of servers.

Abstract: The present disclosure includes a system and method for managing network and server power. In an example of managing network and server power according to the present disclosure, routing network traffic is routed onto a number of core networks based on core network statistics, capacity requirements are determined based on core network statistics for the number of core networks and for a number of servers operating a number of virtual machines on the number of core networks, wherein the number of core networks include a number of core switches and a number of edge switches, and the capacity is set for the number of core switches based on the capacity requirements for the number of core networks and for the number of servers based on the capacity requirements for the number of servers.

Abstract: The invention is a system and method for reconfigurable computers. The invention involves a plurality of reconfigurable component clusters (RCCs), each of which can change their respective configuration upon receiving a configuration command. The invention uses a reconfiguration network for distributing the configuration command to the RCCs, wherein the reconfiguration network comprises a plurality of cells, wherein each RCC is connected to a cell.

Abstract: A computer network (400) includes a first switch (435) and a neighboring switch (440), wherein the first switch (435) floods the computer network (400) as a result of a forwarding table miss and the neighboring switch (440) acts as a barrier to prevent the flood from propagating into unrelated areas of the computer network (400). A method of reducing flooding within a computer network (400) includes intentionally flooding the computer network when a new forwarding table entry is made by a first network switch (435), such that information contained within the new forwarding table entry is recorded by a neighboring network switch (440) which subsequently blocks messages which are received on a proper destination port.

Abstract: A barrier for synchronizing program threads for a plurality of processors includes a filter configured to be coupled to a plurality of processors executing a plurality of threads to be synchronized. The filter is configured to monitor and selectively block fill requests for instruction cache lines. A method for synchronizing program threads for a plurality of processors includes configuring a filter to monitor and selectively block fill requests for instruction cache lines for a plurality of processors executing a plurality of threads to be synchronized.

Abstract: The invention is a system and method for reconfigurable computers. The invention involves a plurality of reconfigurable component clusters (RCCs), each of which can change their respective configuration upon receiving a configuration command. The invention uses a reconfiguration network for distributing the configuration command to the RCCs, wherein the reconfiguration network comprises a plurality of cells, wherein each RCC is connected to a cell.

Abstract: The invention is a system and method for reconfigurable computers. The invention involves a plurality of reconfigurable component clusters (RCCs), each of which can change their respective configuration upon receiving a configuration command. The invention uses a reconfiguration network for distributing the configuration command to the RCCs, wherein the reconfiguration network comprises a plurality of cells, wherein each RCC is connected to a cell.

Abstract: A computer system is provided including a computer having a bus coupled to a computer system memory with a user buffer allocated therein. A network interface controller is coupled between the bus and a network. A retransmit buffer is coupled to the computer system memory, a transmit/receive buffer coupled to the computer system memory, and a retransmit direct memory access is within the network interface controller for moving data between the user buffer and the transmit/receive buffer, the retransmit buffer, or both as well as for moving the data to the network.

Abstract: A computer system with concurrent direct memory access is provided including a computer node having a processor interface bus and a cut-through network interface controller installed on the processor interface bus. A data transfer is initiated through the cut-through network interface controller by starting a direct memory access to move data from a memory to a transmit buffer in the cut-through network interface controller and a network interface controller physical interface transmitting the data, to the computer node attached to a reliable network, before all of the data is in the transmit buffer.

Abstract: A barrier for synchronizing program threads for a plurality of processors includes a filter configured to be coupled to a plurality of processors executing a plurality of threads to be synchronized. The filter is configured to monitor and selectively block fill requests for instruction cache lines. A method for synchronizing program threads for a plurality of processors includes configuring a filter to monitor and selectively block fill requests for instruction cache lines for a plurality of processors executing a plurality of threads to be synchronized.

Abstract: In a method of and system for program thread synchronization, an instruction cache line is determined each of a plurality of program threads to be synchronized. For each processor executing one or more of the threads to be synchronized, execution of the thread is halted at a barrier by rendering the determined instruction cache line unavailable. Execution of the threads resumes by rendering the determined instruction cache lines available.

Abstract: A computer system is provided including a computer having a bus coupled to a computer system memory with a user buffer allocated therein. A network interface controller is coupled between the bus and a network. A retransmit buffer is coupled to the computer system memory, a transmit/receive buffer coupled to the computer system memory, and a retransmit direct memory access is within the network interface controller for moving data between the user buffer and the transmit/receive buffer, the retransmit buffer, or both as well as for moving the data to the network.

Abstract: According to an exemplary embodiment of the present invention, a method for loading data from at least one memory device includes the steps of loading a first value from a first memory location of the at least one memory device, determining a second memory location based on the first value and loading a second value from the second memory location of the at least one memory device, wherein the step of loading a first value is performed by a first processing unit and wherein the steps of determining a second memory location and loading a second value are performed by at least one other processing unit.

Abstract: The invention is a system and method for executing programs. The invention involves a plurality of processing elements, wherein a processing element of the plurality of processing elements generates a branch command. The invention uses a programmable network that transports the branch command from the processing element to one of a first destination processing element by a first programmed transport route and a second destination processing element by a second programmed transport route. The branch command is received and processed by one of the first destination processing element and the second destination processing element, and is not processed by the other of the first processing element and the second processing element.

Abstract: A configurable memory system is disclosed, which includes a processor-to-memory network, a memory-to-processor network, and a plurality of memory modules. Both networks in turns include a plurality of transport cells that can be configured to implement various transport networks, one for a particular memory application. To implement different memory applications in the same configurable memory system, a system designer takes several steps. The system designer identifies memory applications to be implemented in the configurable memory system. For each memory application, the designer allocates a set of memory modules and a transport network carrying data for the memory modules. Each transport network corresponding to a memory application thus establishes the data paths to and from the memory modules for that memory application.

Abstract: One embodiment of the invention is a method for forming a solver for a loop nest of code, the method comprising forming a time and space mapping of a portion of the loop nest, performing at least one optimization that is dependent on the time and space mapping to the portion of the loop nest, and forming a solver from the optimized portion of the loop nest.

Abstract: The invention is a system and method for executing a program that comprises a plurality of basic blocks on a computer system that comprises a plurality of processing elements. The invention generates a branch instruction by one processing element of the plurality of processing elements, sends the branch instruction to the plurality of processing elements. The invention then independently branches to a target of the branch instruction by each of the processing elements of the plurality of processing elements when each processing element receives the sent branch instruction. At least one processing element of the plurality of processing elements receives the branch instruction at a time later than another processing element of the plurality of processing elements.

Abstract: Embodiments of the invention relate to a processing cell for use in computing systems. Generally, a processing cell generates remote instructions to be received and processed by at least one other processing cell. A processing cell may include a program counter, an instruction memory, and appropriate elements such as a branch lookup, a branch unit, etc. Alternatively, the processing cell may include a state machine that replaces the program counter and the instruction memory. Embodiments of the invention are able to support the VLIW mode, the MIMD) mode, a mixture of both modes of execution, etc.